LTM4686B datasheet(18/130 Pages) AD

18 / 130 page

LTM4682

Rev. 0

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PIN FUNCTIONS

serial bus segment, every device must have its unique

subordinate address. If this pin is left open, the LTM4682

powers up to its default subordinate address of 0x4E

(hexadecimal), i.e., 1001110b (industry-standard conven-

tion is used throughout this document: 7-bit subordinate

addressing). The lower 4 bits of the LTM4682’s subor-

dinate address can be altered from this default value by

connecting a resistor from this pin to SGND. Minimize

capacitance—especially when the pin is left open—to

ensure accurate detection of the pin state. It is recom-

mended to use a resistor to set the address. The ASEL_01

address will be used to address Channels 0 and 1, and

a different ASEL_23 address will be used to address

Channels 2 and 3. For addressed ASEL_01, Page 0x00

corresponds to Channel 0 and Page 0x01 corresponds

to Channel 1. See PAGE description section. The GUI will

represent Channel 0 as U0:A0 and Channel 1 as U0:A1.

See the LTpowerPlay Screen Shot (Figure 31).

RUN0, RUN1 (B10, B11 Respectively): Enable Run Input

for Channels 0 and 1, Respectively. Open-drain input and

output. The logic high on these pins enables the respec-

tive outputs of the LTM4682. These open-drain output

pins hold the pin low until the LTM4682 is out of reset

and SVIN_01 is detected to exceed VIN_ON. A pull-up resis-

tor to 3.3V is required in the application. The LTM4682

pulls RUN0 and/or RUN1 low, as appropriate, when a

global fault and/or channel-specific fault occurs whose

fault response is configured to latch off and cease regula-

tion; issuing a CLEAR_FAULTS command through I2C or

power-cycling SVIN_01 is necessary to restart the module,

in such cases. Do not pull RUN logic high with a low

impedance source. The INTVCC is active when SVIN_01 is

above UVLO. This provides power to the VDD33 and VDD25

to allow programming the EEPROM.

SW0 (C1-C2, D1-D2, E1-E2): Switching Node of Channel 0

Step-Down Converter Stage. Used for test purposes or

EMI-snubbing. It may be routed a short distance to a local

test point to monitor the switching action of Channel 0,

if desired, but do not route near any sensitive signals.

Otherwise, leave electrically isolated (open).

VDD25_01 (C8): Internally Generated 2.5V Power Supply

Output Pin for Channels 0 and 1 Circuits. Do not load this

pin with external current; it is used strictly to bias internal

logic and provides current for the internal pull-up resis-

tors connected to the configuration-programming pins.

No external decoupling is required.

VTRIM1_CFG (C9): Output Voltage Select Pin for VOUT1,

Fine Setting. Works in combination with VOUT1_CFG to

affect the VOUT_COMMAND (and associated output volt-

age monitoring and protection/fault-detection thresholds)

of Channel 1, at SVIN_01 power-up. See VOUT1_CFG and

the Applications Information section. A resistor divider

from 2.5V to SGND connected to the pin will set the TRIM

value. See Table 2. Minimize capacitance especially when

the pin is left open to ensure accurate detection of the

pin state. Note that the use of RCONFIGs on VOUT1_CFG/

VTRIM1_CFG can affect the VOUT1 range setting (MFR_

PWM_MODE1[1]) and loop gain. For addressed ASEL_01,

Page 0x00 corresponds to Channel 0 and Page 0x01 cor-

responds to Channel 1. See PAGE description section.

SDA_01, SDA_23 (C10, V8): Serial Bus Data Open-Drain

Input and Output. A pull-up resistor to 3.3V is required in

the application. The SDA_01 is for Channels 0 and 1, and

SDA_23 is for Channels 2 and 3.

ALERT_01, ALERT_23 (C11, W8): Open-Drain Digital

Output. A pull-up resistor to 3.3V is required in the appli-

cation only if SMBALERT interrupt detection is imple-

mented in one’s SMBus system.

SHARE_CLK_01, SHARE_CLK_23 (D8, AA11): Share

Clock, Bidirectional Open-Drain Clock Sharing Pin.

Nominally 100kHz. Used for synchronizing the time

base between multiple LTM4682s (and any other Analog

Devices ICs with a SHARE_CLK pin)—to realize well-

defined rail sequencing and rail tracking. Connect the

SHARE_CLK pins of all such devices together. All devices

with a SHARE_CLK pin will synchronize to the fastest

clock. A pull-up resistor to 3.3V is only required when

synchronizing the time base between devices.

VTRIM0_CFG (D9): Output Voltage Select Pin for VOUT0,

Fine Setting. Works in combination with VOUT0_CFG to

affect the VOUT_COMMAND (and associated output volt-

age monitoring and protection/fault-detection thresholds)

of Channel 0, at SVIN_01 power-up. See VOUT0_CFG and

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