LD5762P datasheet(13/19 Pages) LEADTREND

13 / 19 page

LD5762P

05/02/2017

Leadtrend Technology Corporation

www.leadtrend.com.tw

LD5762P-DS-00 May 2017

more than 50%. To stabilize the control loop, the slope

compensation is required in the traditional UC384X

design by injecting the ramp signal from the RT/CT pin

through a coupling capacitor. LD5762P has internal

slope compensation circuit to simplify the external circuit

design.

Oscillator and Switching Frequency

The LD5762P has the switching frequency between 65

kHz ±6kHz internally to optimize its performance in EMI,

thermal treatment, component sizes and transformer

design.

Dual-Oscillator Green-Mode Operation

There

are

many

different

topologies

has

been

implemented in different chips for the green-mode or

power

saving

requirements

such

“burst-mode

control

”, “skipping-cycle mode”, “variable off-time control

“…etc. The basic operation theory of all these

approaches intended to reduce the switching cycles

under light-load or no-load condition either by skipping

some

switching

pulses

reduce

the

switching

frequency.

By using LD proprietary dual-oscillator technique, the

green-mode frequency can be well controlled and

further to avoid the generation of audible noise.

Frequency Swapping

The LD5762P is built in with frequency swapping

function, which makes it easy for the power supply

designers to optimize EMI performance and system

cost.

On/Off Control

Pulling COMP pin below VZDC will immediately disable

the gate output of LD5762P. Remove the pull-low signal

to reset it.

Over Power Protection (OPP) - Latch Mode

The LD5762P features latch mode of smart OPP

protection. Fig. 13 shows the waveform under fault

condition. The feedback system will force the voltage

loop toward the saturation and thus pull the voltage high

across COMP pin (VCOMP). When the VCOMP ramps

up to the OPP threshold of 4.6V and stays for longer

than OPP delay time, the protection will be activated

and then latch off the gate output to stop switching of the

power circuit. The delay time is to prevent the

false-triggering during power-on, turn-off transient and

in peak load condition. As soon as the over load

condition is removed, the controller will remain latched

until the VCC drops lower than 6V. It is necessary to

restart AC power-on recycling to resume the output.

UVLO(ON)

UVLO(OFF)

AC input Voltage

OUT

Switching

Non- Switching

VCC

4.6V

COMP

PDR

AC Off

AC On( Recycle)

Latch Released

OPP delay time

OPP trip Level

Fig. 13

Over Current Protection (OCP)

–Latch

Mode

When the switching current is higher than the OCP

threshold, the internal counter counts up. When the total

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