ALVD

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WITH VOLTAGE CONTROL

STANDARD SPECIFICATIONS:

APPLICATIONS:

• SONET, xDSL

• SDH, CPE

• STB

FEATURES:

• Based on a proprietary digital multiplier

• Tri-State Output

• Low Phase Jitter

• 2.5V to 3.3V +/- 5% operation

• Ceramic SMD, low profile package

7.0 x 5.0 x 1.8mm

Compliant

PARAMETERS

Frequency Range

750 KHz to 800 MHz

Storage Temperature

-55°C to +125°C

Overall Frequency Stability

±50 PPM max. (see options)

Operating Temperature

0°C to +70°C (see options)

0.3VDC min, 1.65VDC typ, 3.0 VDC max.

3.3V ± 10%

40/60% max.

See options (PECL, CMOS, or LVDS)

Voltage Control (Vcc)

± 50ppm (see option)

Supply Voltage (Vdd)

Output Level

Aging per year

RMS Phase Jitter

Pullability

Tristate Function

Period Jitter (peak to peak)

Phase Noise

±5 ppm max.

Symmetry at 1/2 Vdd

ABRACON P/N

ALVD Series

ABRACON IS

ISO 9001 / QS 9000

CERTIFIED

ABRACON IS

ISO 9001 / QS 9000

CERTIFIED

CERAMIC SMD CRYSTAL CLOCK OSCILLATOR

3ps typical, 5ps max. (12KHz~20MHz)

35 ps typical

-112 dBc/Hz @ 1kHz Offset from 155.52MHz

-125 dBc/Hz @ 10kHz Offset from 155.52MHz

-123 dBc/Hz @ 100KHz Offset from 155.52MHz

-109 dBc/Hz @ 1kHz Offset from 622.08MHz

-110 dBc/Hz @ 10kHz Offset from 622.08MHz

-109 dBc/Hz @ 100KHz Offset from 622.08MHz

"1" (VIH>= 0.7* Vdd) or open: Oscillation

"0" (VIL < 0.3* Vdd) : Hi Z

PECL:

CMOS:

Symmetry (Duty Cycle): 45% min, 50% typ, 55% max,

Rise time: 0.6nSec typ,1.5nS max

Fall time: 0.6nSec typ, 1.5nS max

Output Clock Rise/ Fall Time [10%~90% VDD with 10pF load]: 1.2ns typ, 1.6ns max.

Output Clock Duty Cycle [Measured @ 50% VDD]: 45% min, 50% typical, 55% max

30332 Esperanza, Rancho Santa Margarita, California 92688

Revised: 07.11.07

Visit www.abracon.com for Terms & Conditions of Sale