LTC6906 datasheet(11/28 Pages) AD

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LTC6995-1/LTC6995-2

Rev. B

For more information www.analog.com

tOUT

1/2 tOUT

RST

OUT

LTC6995-1

tRST

tWIDTH

OUT REMAINS HIGH

WHILE RST IS HIGH

tOUT

1/2 tOUT

OUT

LTC6995-2

tRST

tWIDTH

OUT REMAINS HIGH

WHILE RST IS LOW

RST

699512 F04

tOUT

1/2 tOUT

RST

OUT

LTC6995-1

tRST

tWIDTH

OUT REMAINS LOW

WHILE RST IS HIGH

tOUT

1/2 tOUT

OUT

LTC6995-2

tRST

tWIDTH

OUT REMAINS LOW

WHILE RST IS LOW

RST

699512 F03

OPERATION

Reset and Polarity Bit Functions

The Reset input, RST for the LTC6995-1 and RST for the

LTC6995-2, forces the output to a fixed state and resets

the internal clock dividers. The output state when reset is

determined by the polarity bit as selected by through the

DIVCODE setting.

OUTPUT (OSCILLATOR START STATE)

RST/RST POLARITY

LTC6995-1

LTC6995-2

Oscillating (Low)

0 (Reset)

Oscillating (Low)

Oscillating (High)

1 (Reset)

Oscillating (High)

With the POL bit programmed to be 0, the output will be

forced low when reset. When reset is released by chang-

ing state, the oscillator starts. The next rising edge at the

output follows a precise half cycle delay.

With the POL bit programmed to be 1, the output will be

forced high when reset. When reset is released by chang-

ing state, the oscillator starts. The next falling edge at the

output follows a precise half cycle delay.

Figure 3. Reset Timing Diagram (POL Bit = 0)

Figure 4. Reset Timing Diagram (POL Bit = 1)

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