Lattice Semiconductor

ispPAC-POWR6AT6 Data Sheet

19

Figure 14. I

The ispPAC-POWR6AT6 provides 15 registers that can be accessed through its I

vide the user with the ability to monitor and control the device’s inputs and outputs, and transfer data to and from

the device. Table 4 provides a summary of these registers.

Table 4. I

I

Figure 15 shows bit assignments for the ispPAC-POWR6AT6 I

read only bits (cltlock_status.in[1:6]) that reflect the present trim status of individual trim output pins. When a closed

loop-trim controlled power supply's output reaches the value specified by its Profile 0 configuration setting, that trim

output's CLTLOCK_status bit is set to a “1”.

The I

PAC-Designer to operate in SMBus Alert mode, it is set to a “1” by device control logic to send an SMBus Alert.

Logic then waits for it to be acknowledged by a host I

Register Address

Register Name

Read/Write

Description

Value on POR, RESET

0x00

cltlock_status

R/W

Closed-loop trim status

*bit-6 is RW, all others R only

1100 0000

0x01

adc_value_low

R

ADC D[3:0] and status

0000 1110

0x02

adc_value_high

R

ADC D[11:4]

0000 0000

0x03

adc_mux

R/W

ADC Attenuator and MUX[3:0]

1110 1000

0x04

UES_byte0

R

UES[7:0]

EEEE EEEE

0x05

UES_byte1

R

UES[15:8]

EEEE EEEE

0x06

UES_byte2

R

UES[23:16]

EEEE EEEE

0x07

UES_byte3

R

UES[31:24]

EEEE EEEE

0x08

reset

W

Resets device on write

1111 1111

0x09

trim1_trim

R/W

Trim DAC 1 [7:0]

1000 0000

0x0A

trim2_trim

R/W

Trim DAC 2 [7:0]

1000 0000

0x0B

trim3_trim

R/W

Trim DAC 3 [7:0]

1000 0000

0x0C

trim4_trim

R/W

Trim DAC 4 [7:0]

1000 0000

0x0D

trim5_trim

R/W

Trim DAC 5 [7:0]

1000 0000

0x0E

trim6_trim

R/W

Trim DAC 6 [7:0]

1000 0000

Note: x = unknown, 0 = low, 1 = high, E= E

D5

D4

D3

D2

D1

D0

D6

D7

ACK

ACK

ACK

START

123456789

A6

A5

A4

A3

A2

A1

A0

R7

R6

R5

R4

R3

R2

R1

R0

123456789

DEVICE ADDRESS (7 BITS)

REGISTER ADDRESS (8 BITS)

SCL

SDA

R/W

STOP

START

123456789

A6

A5

A4

A3

A2

A1

A0

ACK

123456789

DEVICE ADDRESS (7 BITS)

READ DATA (8 BITS)

SCL

SDA

R/W

STOP

STEP 1: WRITE REGISTER ADDRESS FOR READ OPERATION

STEP 2: READ DATA FROM THAT REGISTER

Note: Shaded Bits Asserted by Slave

OPTIONAL