May 1989

8

Philips Semiconductors

Preliminary specification

TV and VTR stereo/dual sound processor

TDA8415

Control ports

Bus specification

(SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor. Data transfer

may be initiated only when the bus is not busy.

When the bus is free both lines are HIGH. The data on the SDA line must be stable during the HIGH period of the clock.

The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW. The set up and

hold times are specified in the CHARACTERISTICS.

A HIGH-to-LOW transition of the SDA line while SCL is HIGH is defined as the start condition (S). A LOW-to-HIGH

transition of the SDA line while SCL is HIGH is defined as the stop condition (P). The bus receiver will be reset on the

reception of a start condition. The bus is considered to be busy after the start condition. The bus is considered to be free

again after a stop condition.

The first byte is the address and determines whether the TDA8415 is to be read from (status register) or written to (switch

register or mute and port control register).

Fig.4 Address byte.

Where S = start bit and A = acknowledge bit