SCF5249 datasheet(12/56 Pages) FREESCALE

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SCF5249 Integrated ColdFire® Microprocessor Data Sheet, Rev. 3

General Device Information

Freescale Semiconductor

5.23 JTAG

To help with system diagnostics and manufacturing testing, the SCF5249 includes dedicated

user-accessible test logic that complies with the IEEE 1149.1A standard for boundary scan testability,

often referred to as Joint Test Action Group, or JTAG. For more information, refer to the IEEE 1149.1A

standard. Freescale provides BSDL files for JTAG testing.

5.24 System Debug Interface

The ColdFire processor core debug interface supports real-time instruction trace and debug, plus

background-debug mode. A background-debug mode (BDM) interface provides system debug.

In real-time instruction trace, four status lines provide information on processor activity in real time (PST

pins). A four-bit wide debug data bus (DDATA) displays operand data and change-of-flow addresses,

which helps track the machine’s dynamic execution path.

5.25 Crystal and On-chip PLL

Typically, an external 16.92 Mhz or 33.86 Mhz clock input is used for CD R/W applications, while an

11.2896 MHz clock is more practical for Portable CD player applications. However, the on-chip

programmable PLL, which generates the processor clock, allows the use of almost any low frequency

external clock (5-35 Mhz).

Two clock outputs (MCLK1 and MCLK2) are provided for use as Audio Master Clock. The output

frequencies of both outputs are programmable to Fxtal, Fxtal/2, Fxtal/3, and Fxtal/4. The Fxtal/3 option is

only available when the 33.86 Mhz crystal is connected.

The SCF5249 supports VCO operation of the oscillator by means of a 16-bit pulse density modulation

output. Using this mode, it is possible to lock the oscillator to the frequency of an incoming IEC958 or IIS

signal. The maximum trim depends on the type and design of the oscillator. Typically a trim of +/- 100

ppm can be achieved with a crystal oscillator and over +/- 1000 ppm with an LC oscillator.

General Device Information

The SCF5249 is available in a 160-pin MAP BGA package, or a 144-pin QFP package.

Documentation

Table 3 lists the documents that provide a complete description of the SCF5249 and are required to design

properly with the part. Documentation is available from a local Freescale distributor, a Freescale

semiconductor sales office, a Freescale Literature Distribution Center, or through the Freescale DSP home

page on the internet; http://www.freescale.com/

(the source for the latest information).

SCF5249 Datasheet(PDF) 12 Page - Freescale Semiconductor, Inc