PS810 datasheet(38/46 Pages) MICROCHIP

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PS810

DS21904C-page 38

TABLE 10-3:

AC CHARACTERISTICS (TA = -20°C TO +85°C; VDD (INTERNAL) = +2.8V ±7%)

TABLE 10-4:

AC CHARACTERISTICS – SMBus/I2C™ (TA = -20°C TO +85°C;

VDD (INTERNAL) = +2.8V ±7%)

Symbol

Description

Min.

Typ.

Max.

Units

Condition

fRC

Internal RC Oscillator Frequency

509.952

512

514.048

kHz

fA/D

Internal A/D Operating Clock

—

fRC/16

—

kHz

tPOR

Power-on Reset Delay

—

Delay from time when VC1

voltage exceeds 2.7V

tSHELF

Delay to Entry of Shelf-Sleep mode

—

tWAKE

Delay to Exit of Shelf-Sleep mode

—

SDA and SCL go high

Symbol

Description

Min.

Typ.

Max.

Units

Condition

fSMB

SMBus Clock Operating Frequency

—

100

kHz

Slave mode

tBUF

Bus Free Time between Start and Stop

4.7

—

μs

tSHLD

Bus Hold Time after Repeated Start

4.0

—

μs

tSU:STA

Setup Time before Repeated Start

4.7

—

μs

tSU:STOP

Stop Setup Time

4.0

—

μs

tHLD

Data Hold Time

—

tSETUP

Data Setup Time

250

—

tLOW

Clock Low Period

4.7

—

μs

tHIGH

Clock High Period

4.0

—

μs

(Note 2)

tLOW:SEXT

Message Buffering Time

—

(Notes 1, 3)

tHIGH:MEXT

Message Buffering Time

—

(Notes 1, 4)

Clock/Data Fall Time

—

300

(Note 5)

Clock/Data Rise Time

—

1000

(Note 5)

Note 1:

The PS810 will time-out when the cumulative message time defined from Start-to-Ack, Ack-to-Ack or

Ack-to-Stop exceeds the value of TTIMEOUT, min. of 25 ms. The PS810 will reset the communication no

later than TTIMEOUT, max. of 35 ms.

tHIGH max. provides a simple, ensured method for devices to detect bus Idle conditions.

tLOW:SEXT is the cumulative time a slave device is allowed to extend the clock cycles in one message from

the initial start to the stop.

tHIGH:MEXT is the cumulative time a master device is allowed to extend its clock cycles within each byte of

a message as defined from Start-to-Ack, Ack-to-Ack or Ack-to-Stop.

Rise and fall time is defined as follows:

tR = (VILMAX – 0.15) to (VIHMIN + 0.15)

tF = 0.9 VDD to (VILMAX – 0.15)

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