2

February 2007

Document Control #ML0004 Rev 0.3

STK22C48

PIN CONFIGURATIONS

PIN NAMES

Pin Name

I/O

Description

Input

Address: The 11 address inputs select one of 2,048 bytes in the nvSRAM array

I/O

Data: Bi-directional 8-bit data bus for accessing the nvSRAM

E

Input

Chip Enable: The active low E input selects the device

W

Input

Write Enable: The active low W enables data on the DQ pins to be written to the address

location latched by the falling edge of E

G

Input

Output Enable: The active low G input enables the data output buffers during read cycles.

De-asserting G high caused the DQ pins to tri-state.

Power Supply

Power: 5.0V, ±10%

Power Supply

Ground

NC

HSB

NC

G

W

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

E

28-pin 300 mil SOIC

28-pin 330 mil SOIC