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TDA8752 Datasheet(PDF) 26 Page - NXP Semiconductors |
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TDA8752 Datasheet(HTML) 26 Page - NXP Semiconductors |
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26 / 36 page  1999 Mar 09 26 Philips Semiconductors Product specification Triple high speed Analog-to-Digital Converter (ADC) TDA8752 Data timing (see Fig.11); fCLK = 100 MHz; CL = 10 pF; note 2 td(s) sampling delay time referenced to CKADCO −− − ns td(o) output delay time −−3.3 −2.6 ns th(o) output hold time 4.6 5.5 − ns 3-state output delay time; (see Fig.12) tdZH output enable HIGH − 12 − ns tdZL output enable LOW − 10 − ns tdHZ output disable HIGH − 50 − ns tdLZ output disable LOW − 65 − ns PLL clock output VOL LOW-level output voltage Io =1mA − 0.3 0.8 V VOH HIGH-level output voltage Io = − 1 mA 2.4 3.5 − V IOL LOW-level output current VOL = 0.4 V − 2 − mA IOH HIGH-level output current VOH = 2.7 V −−0.4 − mA ADC data outputs VOL LOW-level output voltage Io =1mA − 0 0.8 V VOH HIGH-level output voltage Io = − 1 mA 2.4 VCCD − V IOL LOW-level output current VOL = 0.4 V − 2 − mA IOH HIGH-level output current VOH = 2.7 V −−0.5 − mA TTL digital inputs (CKREF, COAST, CKEXT, INV, HSYNC and CLP) VIL LOW level input voltage −− 0.8 V VIH HIGH level input voltage 2.0 −− V IIL LOW level input current VIL = 0.4 V 400 −− µA IIH HIGH level input current VIH = 2.7 V −− 100 µA Zi input impedance − 4 − k Ω Ci input capacitance − 4.5 − pF 3-wire serial bus treset reset time of the chip before 3-wire communication − 600 − ns tsu data set-up time − 100 − ns th data hold time − 100 − ns I2C-bus; see note 3 fSCL clock frequency 0 − 100 kHz tBUF time the bus must be free before new transmission can start 4.7 −− µs SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT |
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