TDA8753 datasheet(8/20 Pages) PHILIPS

8 / 20 page

1996 Jan 12

Philips Semiconductors

Product speciﬁcation

YUV 8-bit analog-to-digital interface

TDA8753A

Clamp and references [Iref, DECref(L) and Vref(H)]

ACL

clamping accuracy

−4

−

LSB

U and V

−1

−

LSB

Cclamp

serial clamp capacitor

−

ZADC

internal impedance between

pin 29 and VSSA

−

420

−Ω

Vref(H)

converter reference HIGH, applied

to pin 29

−

2.38

−

VDECref(L)

converter reference voltage LOW,

applied to pin 28

Vref(H) = 2.38 V

−

0.39

−

Y analog input (INY); Vref(H) = 2.38 V, Vref(L) = 0.39 V; see Table 4

Vi(p-p)

input voltage, full range

(peak-to-peak value)

ramp input

−

1.26

−

input current

clamp non-active

−

100

input capacitance

−−

U,V analog inputs (INU and INV); Vref(H) = 2.38 V, Vref(L) = 0.39 V; see Table 4

Vi(p-p)

input voltage (peak-to-peak value) ramp input

−

1.26

−

input current

clamp non-active

−

100

input capacitance

−−

Inputs isolation

αact

crosstalk between INY, INU and

INV

−−−50

Digital outputs (Y0 to Y7, U1, U0, V1 and V0); see Table 3

VOL

LOW level output voltage

IOL = 1.6 mA

−

0.5

VOH

HIGH level output voltage

IOH = 0.4 mA

2.4

−

VDDD

Analog signal processing (fCLK = 20 MHz)

Gdiff

differential gain

note 2

−

1.5

−

Φdiff

differential phase

note 2

−

1.0

−

deg

fall

harmonics (full scale) all

components

note 3; Y

−−53

−

U and V

−−55

−

SVR

supply voltage ripple rejection

note 4

−

%/V

bandwidth

−1 dB; note 5

−

MHz

Transfer function (fclk = 16 MHz)

INL

integral non-linearity

ramp input

−±0.75

−

LSB

DNL

differential non-linearity

ramp input; Y

−±0.5

±0.75

LSB

ramp input; U and V

−±0.6

±0.9

LSB

SNR

signal-to-noise ratio without

harmonics

note 6; Y

44.5

−

U and V

−

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

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