TDA8755 datasheet(8/20 Pages) PHILIPS

8 / 20 page

1995 Mar 09

Philips Semiconductors

Product speciﬁcation

YUV 8-bit video low-power

analog-to-digital interface

TDA8755

Notes

1. Low frequency ramp signal (VI(p-p) = full-scale and 64 µs period) combined with a sinewave input voltage

(VI(p-p) = 0.25 full-scale, fi = maximum permitted frequency) at the input.

2. The input conditions are related as follows:

a) Y channel: VI(p-p) = 1.0 V; fi = 4.43 MHz

b) U/V channel: VI(p-p) = 1.0 V; fi = 1.5 MHz.

3. Supply voltage ripple rejection:

a) SVRR1 is the variation of the input voltage producing output code 127 (code 15) for supply voltage variation

of 0.5 V:

b) SVRR2 is the relative variation of the full-scale range of analog input for a supply voltage variation of 0.5 V:

4. Full-scale sinewave (fi = 4.43 MHz for Y and fi = 1.5 MHz for U and V; fclk = 20 MHz).

5. The number of effective bits is measured using a 20 MHz clock frequency. This value is given for a 4.43 MHz input

frequency on the Y channel (1.5 MHz on the U and V channels). This value is obtained via a Fast Fourier Transform

(FFT) treatment taking 4

× Tclk (clock periods) acquisition points per period. The calculation takes into account all

harmonics and noise up to half of the clock frequency (NYQUIST frequency).

Conversion to signal-to-noise ratio: S/N = EB

× 6.02 + 1.76 dB.

6. Output data acquisition is available after the maximum delay time of td.

7. U and V output data is not valid during tCLP.

Timing (fclk = 20 MHz); note 6; see Figs 3 to 7

tds

sampling delay time

−

output hold time

−−

output delay time

−

tdZH

3-state output delay time

enable-to-HIGH

−

tdZL

3-state output delay time

enable-to-LOW

−

tdHZ

3-state output delay time

disable-to-HIGH

−

811

tdLZ

3-state output delay time

disable-to-LOW

−

46ns

clock rise time

−

clock fall time

−

tsu

HREF set-up time

−−

HREF hold time

−−

data output rise time

−

data output fall time

−

tCLP

minimum time for active clamp

note 7; see Fig.9

−−µs

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

SVRR1

20 log

∆V

I127

()

∆V

CCA

----------------------

SVVR2

∆ V

()

I255

()

–

()

I 255

()

–

------------------------------------------------

∆V

CCA

------------------

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