TDA8790 datasheet(8/20 Pages) PHILIPS

8 / 20 page

1996 Feb 21

Philips Semiconductors

Product speciﬁcation

8-bit, 40 Msps 2.7 to 5.5 V universal

analog-to-digital converter

TDA8790

Notes

1. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock

must not be less than 1 ns.

2. Analog input voltages producing code 0 up to and including 256:

a) VosB (voltage offset BOTTOM) is the difference between the analog input which produces data equal to 00 and

the reference voltage BOTTOM (VRB) at Tamb =25 °C.

b) VosT (voltage offset TOP) is the difference between VRT (reference voltage TOP) and the analog input which

produces data outputs equal to 256 at Tamb =25 °C.

SIGNAL-TO-NOISE RATIO; see Fig.9; note 6

S/N

signal-to-noise ratio (full scale)

without harmonics;

fclk = 40 MHz;

fi = 4.43 MHz

−

EFFECTIVE BITS; see Fig.9; note 6

effective bits

fclk = 40 MHz

fi = 300 kHz

−

7.8

−

bits

fi = 4.43 MHz

−

7.3

−

bits

DIFFERENTIAL GAIN; see note 7

Gdiff

differential gain

fclk = 40 MHz;

PAL modulated ramp

−

1.5

−

DIFFERENTIAL PHASE; see note 7

ϕdiff

differential phase

fclk = 40 MHz;

PAL modulated ramp

−

0.25

−

deg

Timing (fclk = 40 MHz; CL = 20 pF); see Fig.4; note 8

tds

sampling delay time

−−

5ns

output hold time

−−

output delay time

VDDO = 4.75 V

VDDO = 3.15 V

VDDO = 2.7 V

3-state sleep mode delay times; see Fig.5

tdZH

enable HIGH

−

tdZL

enable LOW

−

tdHZ

disable HIGH

−

tdLZ

disable LOW

−

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

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