TDA8793 datasheet(8/20 Pages) PHILIPS

8 / 20 page

1999 Oct 06

Philips Semiconductors

Preliminary speciﬁcation

8-bit, low-power, 3 V, 100 Msps

Analog-to-Digital Converter (ADC)

TDA8793

Analog signal processing; note 3; see Figs 4, 5, 6 and 7

INL

integral non-linearity

ramp input; fCLK = 2 MHz;

VCCA =VCCD =3V

−±0.8

tbf

LSB

DNL

differential non-linearity

ramp input; fCLK = 2 MHz;

VCCA =VCCD =3V

−±0.25

tbf

LSB

S/N

signal-to-noise ratio (full scale)

without harmonics;

fCLK = 100 MHz

fi = 20 MHz

−

fi = 50 MHz

−

BW(−3dB)

−3 dB analog bandwidth

−

350

−

MHz

THD

total harmonics distortion

fi = 20 MHz

−−56

−

fi = 50 MHz

−−52

−

Hfund(FS)

full scale fundamental harmonics

fCLK = 100 MHz

fi = 20 MHz

−−

0dB

fi = 50 MHz

−−

0dB

HD2(FS)

second harmonic distortion (full

scale) all components included

differential inputs;

fCLK = 100 MHz

fi = 20 MHz

−

fi = 50 MHz

−

single-ended input;

fCLK = 100 MHz

fi = 20 MHz

−

fi = 50 MHz

−

HD3(FS)

third harmonic distortion (full scale)

all components included

differential inputs;

fCLK = 100 MHz

fi = 20 MHz

−

fi = 50 MHz

−

single-ended input;

fCLK = 100 MHz

fi = 20 MHz

−

fi = 50 MHz

−

SFDR

spurious free dynamic range

fCLK = 100 MHz

fi = 20 MHz

−

fi = 50 MHz

−

effective bits

fCLK = 100 MHz; note 4

bits

fi = 20 MHz

7.0

7.4

−

bits

fi = 50 MHz

−

7.2

−

bits

Data timing; fCLK = 100 MHz; CL =10pF; see Fig.8

tds

sampling delay

−−

1.5

output hold time

−−

output delay time

−

58ns

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

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