5M570Z datasheet(13/72 Pages) ALTERA

13 / 72 page

Chapter 2: MAX V Architecture

2–7

Logic Array Blocks

December 2010

Altera Corporation

MAX V Device Handbook

With the LAB-wide addnsub control signal, a single LE can implement a one-bit adder

and subtractor. This signal saves LE resources and improves performance for logic

functions such as correlators and signed multipliers that alternate between addition

and subtraction depending on data.

The LAB column clocks [3..0], driven by the global clock network, and LAB local

interconnect generate the LAB-wide control signals. The MultiTrack interconnect

structure drives the LAB local interconnect for non-global control signal generation.

The MultiTrack interconnect’s inherent low skew allows clock and control signal

distribution in addition to data signals. Figure 2–5 shows the LAB control signal

generation circuit.

Figure 2–5. LAB-Wide Control Signals

labclkena1

labclk2

labclk1

labclkena2

asyncload

or labpre

syncload

Dedicated

LAB Column

Clocks

Local

Interconnect

Local

Interconnect

Local

Interconnect

Local

Interconnect

Local

Interconnect

Local

Interconnect

labclr1

labclr2

synclr

addnsub

5M570Z Datasheet(PDF) 13 Page - Altera Corporation

5M570Z Datasheet(HTML) 13 Page - Altera Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72

Datasheet Download

Link URL