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PIC18F4321 Datasheet(PDF) 175 Page - Microchip Technology

Part # PIC18F4321
Description  28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology
PDF  396 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

PIC18F4321 Datasheet(HTML) 175 Page - Microchip Technology

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© 2007 Microchip Technology Inc.
Preliminary
DS39689E-page 173
PIC18F4321 FAMILY
REGISTER 17-5:
SSPCON2: MSSP CONTROL REGISTER 2 (I2C™ MODE)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
GCEN
ACKSTAT
ACKDT/
ADMSK5
ACKEN(1)/
ADMSK4
RCEN(1)/
ADMSK3
PEN(1)/
ADMSK2
RSEN(1)/
ADMSK1
SEN(1)
bit 7
bit 0
bit 7
GCEN: General Call Enable bit (Slave mode only)
1
= Enable interrupt when a general call address (0000h) is received in the SSPSR
0
= General call address disabled
bit 6
ACKSTAT: Acknowledge Status bit (Master Transmit mode only)
1
= Acknowledge was not received from slave
0
= Acknowledge was received from slave
bit 5
ACKDT/ADMSK5: Acknowledge Data bit
In Master Receive mode:
1
= Not Acknowledge
0
= Acknowledge
Note:
Value that will be transmitted when the user initiates an Acknowledge sequence at
the end of a receive.
In Slave mode:
1
= Address masking of ADD5 enabled
0
= Address masking of ADD5 disabled
bit 4
ACKEN/ADMSK4: Acknowledge Sequence Enable bit
In Master Receive mode:(1)
1
= Initiate Acknowledge sequence on SDA and SCL pins and transmit ACKDT data bit.
Automatically cleared by hardware.
0
= Acknowledge sequence Idle
In Slave mode:
1
= Address masking of ADD4 enabled
0
= Address masking of ADD4 disabled
bit 3
RCEN/ADMSK3: Receive Enable bit
In Master Receive mode:(1)
1
= Enables Receive mode for I2C
0
= Receive Idle
In Slave mode:
1
= Address masking of ADD3 enabled
0
= Address masking of ADD3 disabled
bit 2
PEN/ADMSK2: Stop Condition Enable bit
In Master mode:(1)
1
= Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.
0
= Stop condition Idle
In Slave mode:
1
= Address masking of ADD2 enabled
0
= Address masking of ADD2 disabled
bit 1
RSEN/ADMSK1: Repeated Start Condition Enable bit
In Master mode:(1)
1
= Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.
0
= Repeated Start condition Idle
In Slave mode (7-bit Address mode):
1
= Address masking of ADD1 enabled
0
= Address masking of ADD1 disabled
In Slave mode (10-bit Address mode):
1
= Address masking of ADD1 and ADD0 enabled
0
= Address masking of ADD1 and ADD0 disabled



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