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PIC18F4321 Datasheet(PDF) 176 Page - Microchip Technology

Part # PIC18F4321
Description  28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology
PDF  396 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

PIC18F4321 Datasheet(HTML) 176 Page - Microchip Technology

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PIC18F4321 FAMILY
DS39689E-page 174
Preliminary
© 2007 Microchip Technology Inc.
REGISTER 17-5:
SSPCON2: MSSP CONTROL REGISTER 2 (I2C™ MODE) – CONTINUED
REGISTER 17-6:
SSPADD: MSSP ADDRESS REGISTER(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
GCEN
ACKSTAT
ACKDT/
ADMSK5
ACKEN(1)/
ADMSK4
RCEN(1)/
ADMSK3
PEN(1)/
ADMSK2
RSEN(1)/
ADMSK1
SEN(1)
bit 7
bit 0
bit 0
SEN: Start Condition Enable/Stretch Enable bit(1)
In Master mode:
1
= Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.
0
= Start condition Idle
In Slave mode:
1
= Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0
= Clock stretching is disabled
Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is active, these bits
may not be set (no spooling) and the SSPBUF may not be written (or writes to the
SSPBUF are disabled).
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ADD7
ADD6
ADD5
ADD4
ADD3
ADD2
ADD1
ADD0
bit 7
bit 0
bit 7-0
ADD<7:0>: MSSP Address bits
Note 1: MSSP Address register in 12C Slave mode. MSSP Baud Rate register in I2C Master
mode.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown



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