DP83867IRPAP datasheet(7/139 Pages) TI1

7 / 139 page

Table 5-1. Pin Functions (continued)

TYPE(1)

DESCRIPTION

NAME

HTQFP

VQFN

GENERAL PURPOSE I/O

GPIO_0

S, O, PD

General Purpose I/O: This signal provides a multi-function configurable I/O.

Please refer to the GPIO_MUX_CTRL register for details.

GPIO_1

S, O, PD

General Purpose I/O: This signal provides a multi-function configurable I/O.

Please refer to the GPIO_MUX_CTRL register for details.

MANAGEMENT INTERFACE

MDC

I, PD

MANAGEMENT DATA CLOCK: Synchronous clock to the MDIO serial

management input/output data. This clock may be asynchronous to the MAC

transmit and receive clocks. The maximum clock rate is 25MHz and no

minimum.

MDIO

I/O

MANAGEMENT DATA I/O: Bi-directional management instruction/data signal

that may be sourced by the management station or the PHY. This pin requires

pullup resistor. The IEEE specified resistor value is 1.5kΩ, but a 2.2kΩ is

acceptable.

INT / PWDN

I/O, PU

INTERRUPT / POWER DOWN:

The default function of this pin is POWER DOWN.

POWER DOWN: Asserting this signal low enables the Power Down mode of

operation. In this mode, the device will power down and consume minimum

power. Register access will be available through the Management Interface to

configure and power up the device.

INTERRUPT: This pin may be programmed as an interrupt output instead of

a Power down input. In this mode, Interrupts will be asserted low using this

pin. When operating this pin as an interrupt, it is an open-drain architecture.

When operating this pin as an interrupt, an external 2.2kΩ connected to the

VDDIO supply is recommended.

RESET

RESET_N

I, PU

RESET: The active low RESET initializes or re-initializes the DP83867. All

internal registers will re-initialize to their default state upon assertion of

RESET. The RESET input must be held low for a minimum of 1µs.

CLOCK INTERFACE

CRYSTAL/OSCILLATOR INPUT: 25MHz oscillator or crystal input (50 ppm)

CRYSTAL OUTPUT: Second terminal for 25MHz crystal. Must be left floating

if a clock oscillator is used.

CLK_OUT

CLOCK OUTPUT: Output clock

JTAG INTERFACE

JTAG_CLK

I, PU

JTAG TEST CLOCK: IEEE 1149.1 Test Clock input, primary clock source for

all test logic input and output controlled by the testing entity.

JTAG_TDO

JTAG TEST DATA OUTPUT: IEEE 1149.1 Test Data Output pin, the most

recent test results are scanned out of the device via TDO.

JTAG_TMS

I, PU

JTAG TEST MODE SELECT: IEEE 1149.1 Test Mode Select pin, the TMS

pin sequences the Tap Controller (16-state FSM) to select the desired test

instruction.

JTAG_TDI

I, PU

JTAG TEST DATA INPUT: IEEE 1149.1 Test Data Input pin, test data is

scanned into the device via TDI.

JTAG_TRSTN

I, PU

JTAG TEST RESET: IEEE 1149.1 Test Reset pin, active low reset provides

for asynchronous reset of the Tap Controller. This reset has no effect on the

device registers.

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DP83867IR, DP83867CR

SNLS484H – FEBRUARY 2015 – REVISED JUNE 2024

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