AD7841 datasheet(12/12 Pages) AD

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AD7841

REV. 0

–12–

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

44-Lead MQFP (S-44)

0.548 (13.925)

0.546 (13.875)

TOP VIEW

(PINS DOWN)

0.033 (0.84)

0.029 (0.74)

0.398 (10.11)

0.390 (9.91)

0.016 (0.41)

0.012 (0.30)

0.083 (2.11)

0.077 (1.96)

0.040 (1.02)

0.032 (0.81)

0.040 (1.02)

0.032 (0.81)

SEATING

PLANE

0.096 (2.44)

MAX

0.037 (0.94)

0.025 (0.64)

8°

0.8°

GND

VDD

8/10-BIT

DAC

GND

VDD

8/10-BIT

DAC

LOGIC LEVEL

SHIFT

+5V

SCLK

D IN

FSIN/CS

SCLK

D IN

FSIN/CS

0V TO +5V

0V TO

VREF(+)AB

A0, A1, A2

VOUTA

VOUTB

VREF( )AB

AD7841*

GND

DATA BUS

ADDR

DECODER

ADDR BUS

SDATA

SCLK

DATA BUS

CONTROLLER

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 22. Programmable Reference Generation for the AD7841

The AD8803 has an output voltage range of GND to VDD (0 V

to +5 V). To trim the VREF(+) input, the appropriate trim range

on the AD8803 DAC can be set using the VREFL and VREFH pins

allowing 8 bits of resolution between the two points. This will

allow the VREF(+) pin to be adjusted to remove gain errors.

To trim the VREF(–) voltage, some method of providing a trim

voltage in the required negative voltage range is required. Nei-

ther the AD7804 or the AD8803 can provide this range in nor-

mal operation as their output range is 0 V to +5 V. There are

two methods of producing this negative voltage. One method is

to provide a positive output voltage and then to level shift that

analog voltage to the required negative range. Alternatively

these DACs can be operated with supplies of 0 V and –5 V, with

the VDD pin connected to 0 V and the GND pin connected to

–5 V. Now these can be used to provide the negative reference

voltages for the VREF(–) inputs on the AD7841. However, the

digital signals driving the DACs need to be level-shifted from

the 0 V to +5 V range to the –5 V to 0 V range. Figure 22 shows

a typical application circuit to provide programmable reference

capabilities for the AD7841.

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