Ultraprecision Operational Amplifier

Data Sheet

OP177

Rev. H

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FEATURES

Ultralow offset voltage

TA = 25°C, 25 μV maximum

Outstanding offset voltage drift 0.3 μV/°C maximum

Excellent open-loop gain and gain linearity

12 V/μV typical

CMRR: 130 dB minimum

PSRR: 115 dB minimum

Low supply current 2.0 mA maximum

Fits industry-standard precision operational amplifier

sockets

PIN CONFIGURATION

8

7

6

5

1

2

3

4

NC = NO CONNECT

–IN

+IN

V+

OUT

NC

V–

VOS TRIM

VOS TRIM

OP177

TOP VIEW

(Not to Scale)

Figure 1. 8-Lead PDIP (P-Suffix),

8-Lead SOIC (S-Suffix)

GENERAL DESCRIPTION

The OP177 features one of the highest precision performance of

any operational amplifier currently available. Offset voltage of the

OP177 is only 25 μV maximum at room temperature. The ultralow

VOS of the OP177 combines with the exceptional offset voltage

drift (TCVOS) of 0.3 μV/°C maximum to eliminate the need for

external VOS adjustment and increases system accuracy over

temperature.

The OP177 open-loop gain of 12 V/μV is maintained over the full

±10 V output range. CMRR of 130 dB minimum, PSRR of 120 dB

minimum, and maximum supply current of 2 mA are just a few

examples of the excellent performance of this operational amplifier.

The combination of outstanding specifications of the OP177

ensures accurate performance in high closed-loop gain

applications.

This low noise, bipolar input operational amplifier is also a cost

effective alternative to chopper-stabilized amplifiers. The OP177

provides chopper-type performance without the usual problems

of high noise, low frequency chopper spikes, large physical size,

limited common-mode input voltage range, and bulky external

storage capacitors.

The OP177 is offered in the −40°C to +85°C extended industrial

temperature ranges. This product is available in 8-lead PDIP, as

well as the space saving 8-lead SOIC.

FUNCTIONAL BLOCK DIAGRAM

2B

C1

R7

(OPTIONAL NULL)

Q19

R2B*

R2A*

R1B

R1A

R9

R10

OUTPUT

R8

R6

C3

C2

Q13

Q17

R5

Q27

Q26

Q25

Q8

Q7

Q23

Q24

Q21

Q22

Q9

Q4

Q6

Q3

Q5

R3

R4

Q1

Q2

Q11

Q12

Q14

Q10

Q16

Q15

Q18

Q20

V+

V–

NONINVERTING

INPUT

INVERTING

INPUT

*R2A AND R2B ARE ELECTRONICALLY ADJUSTED ON CHIP AT FACTORY.

Figure 2. Simplified Schematic