TSA5522M datasheet(3/20 Pages) PHILIPS

3 / 20 page

1996 Jan 23

Philips Semiconductors

Product speciﬁcation

1.4 GHz I2C-bus controlled synthesizer

TSA5522

QUICK REFERENCE DATA

Note

1. One band switch buffer ON; Io = 20 mA.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

VCC1

supply voltage (+5 V)

4.5

−

5.5

VCC2

band switch supply voltage (+12 V)

VCC1

13.5

ICC1

supply current

−

ICC2

band switch supply current

note 1

−

fRF

RF input frequency

−

1400

MHz

Vi(RF)

RF input voltage

fi = 80 to 150 MHz

− 25

−

dBm

fi = 150 to 1000 MHz

− 28

−

dBm

fi = 1000 to 1400 MHz

− 26

−

dBm

fxtal

crystal oscillator input frequency

−

MHz

Io(PNP)

PNP band switch buffers output current

−

Io(NPN)

NPN open-collector output current

−

Tamb

operating ambient temperature

−20

−

+85

°C

Tstg

storage temperature (IC)

−40

−

+150

°C

GENERAL DESCRIPTION (see Fig.1)

The device is a single chip PLL frequency synthesizer

designed for TV and VCR tuning systems. The circuit

consists of a divide-by-eight prescaler with its own

preamplifier, a 15-bit programmable divider, a crystal

oscillator and its programmable reference divider and a

phase/frequency detector combined with a charge-pump

which drives the tuning amplifier, including 33 V output.

Three high-current PNP band switch buffers are provided

for band switching together with four open-collector NPN

outputs (only one open-collector output on 16-pin

devices). These ports can also be used as input ports [one

Analog-to Digital Converter (ADC) and three general

purpose I/O ports (not available on 16-pin devices)]. An

output is provided to control a Philips mixer/oscillator IC in

combination with the PNP buffers state.

Depending on the reference divider ratio (512, 640

or 1024), the phase comparator operates at 3.90625 kHz,

6.25 kHz or 7.8125 kHz with a 4 MHz crystal. The LOCK

detector bit FL is set to logic 1 when the loop is locked and

is read on the SDA line (status byte) during a read

operation.

The ADC is available for digital AFC control. The ADC

code is read during a read operation on the I2C-bus. The

ADC input is combined with the port P6. In the TEST

mode, this port is also used as a TEST output for fref and

⁄2fdiv (see Table 4).

I2C-bus format

Five serial bytes (including address byte) are required to

address the device, select the VCO frequency, program

the ports, set the charge-pump current and the reference

divider ratio. The device has three independent I2C-bus

addresses selected by applying a specific voltage on AS

input (see Table 3). The general address C2 is always

valid.

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