MP6546

– 22V, 3A PEAK, 3-PHASE BLDC DRIVER WITH 1MHZ I2C INTERFACE

MP6546 Rev. 1.0

MonolithicPower.com

15

3/20/2023

MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.

© 2023 MPS. All Rights Reserved.

REGISTER MAP (6)

Add.

Type

H/L

Default

Bit[7]

Bit[6]

Bit[5]

Bit[4]

Bit[3]

Bit[2]

Bit[1]

Bit[0]

00h

OTP

H

E0h

OCP_

EN

SCP_

EN

STDBY_

EN

ADDR[1:0]

OCP_

SEL

AMOD

THETA_

DIR

L

03h

OVP_

EN

FLT_N_SVM[1:0]

DRV_

MOD

SPI_3

FLT_N[2:0]

01h

OTP

H

51h

VA_BIAS[7:0]

L

51h

VB_BIAS[7:0]

02h

OTP

H

00h

THETA_BIAS[11:4]

L

07h

THETA_BIAS[3:0]

POLE_PAIR[3:0]

03h

OTP

H

01h

SPI_BAUD[2:0]

RESERVED

TRIM_

ENP

L

00h

PCODE[7:0]

07h

RAM

H

00h

RESERVED

ANGLE_T[11:8]

L

00h

ANGLE_T[7:0]

08h

RAM

H

00h

RESERVED

UD[9:8]

L

00h

UD[7:0]

09h

RAM

H

00h

RESERVED

UQ[9:8]

L

00h

UQ[7:0]

0Ah

RAM

H

08h

RESERVED

ALN_MD

RESERVED

L

00h

RESERVED

0Ch

RO

H

-

FAULT

ANGLE[14:8]

L

-

ANGLE[7:0]

0Dh

RO

H

-

RESERVED

SCPF

TSDF

OVPF

OCPF

L

-

INL_COMP[7:0]

0Fh

CMD

H

-

NOR_MOD

L

-

10h

CMD

H

-

STB_MOD

L

-

11h

RAM

H

00h

CMD_CODE[2:0]

SPI_REG_ADDR[4:0]

L

00h

SPI_DATA[7:0]

13h

RAM

H

00h

INL_02[3:0]

INL_01[5:2]

L

00h

INL_01[1:0]

INL_00[5:0]

14h

RAM

H

00h

INL_05[1:0]

INL_04[5:0]

L

00h

INL_03[5:0]

INL_02[5:4]

15h

RAM

H

00h

INL_07[5:0]

INL_06[5:4]

L

00h

INL_06[4:0]

INL_05[5:2]

16h

RAM

H

00h

INL_0A[3:0]

INL_09[5:2]

L

00h

INL_09[1:0]

INL_08[5:0]

17h

RAM

H

00h

INL_0D[1:0]

INL_0C[5:0]

L

00h

INL_0B[5:0]

INL_0A[5:4]

18h

RAM

H

00h

INL_0F[5:0]

INL_0E[5:4]

L

00h

INL_0E[4:0]

INL_0D[5:2]

19h

RAM

H

00h

INL_12[3:0]

INL_11[5:2]

L

00h

INL_11[1:0]

INL_10[5:0]

1Ah

RAM

H

00h

INL_15[1:0]

INL_14[5:0]

L

00h

INL_13[5:0]

INL_12[5:4]

1Bh

RAM

H

00h

INL_17[5:0]

INL_16[5:4]

L

00h

INL_16[4:0]

INL_15[5:2]

1Ch

RAM

H

00h

INL_1A[3:0]

INL_19[5:2]

L

00h

INL_19[1:0]

INL_18[5:0]

1Dh

RAM

H

00h

INL_1D[1:0]

INL_1C[5:0]

L

00h

INL_1B[5:0]

INL_1A[5:4]

1Eh

RAM

H

00h

INL_1F[5:0]

INL_1E[5:4]

L

00h

INL_1E[4:0]

INL_1D[5:2]

Note:

6)

In the H/L column, “H” means bits[15:8], while “L” means bits[7:0].