CS5101A datasheet(6/39 Pages) CIRRUS

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CS5101A CS5102A

DS45F6

SWITCHING CHARACTERISTICS, CS5101A

(TA = TMIN to TMAX; VA+, VD+ = 5V ±10%; VA-, VD- = -5V ±10%; Inputs: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF).

Notes: 12. External loading capacitors are required to allow the crystal to oscillate. Maximum crystal frequency is 8.0 MHz in

FRN mode (100 kSps).

13. With an 8.0 MHz crystal, two 10 pF loading capacitors and a 10 M

Ω parallel resistor (see Figure 9).

14. These timings are for FRN mode.

15. SSH only works correctly if

HOLD falling edge is within +15 to +30 ns of CH1/2 edge or if CH1/2 edge occurs after

HOLD rises to 64tclk after HOLD has fallen. These timings are for PDT and RBT modes.

16. When

HOLD goes low, the analog sample is captured immediately. To start conversion, HOLD must be latched

by a falling edge of CLLKIN. Conversion will begin on the next rising edge of CLKIN after

HOLD is latched. If HOLD

is operated synchronous to CLKIN, the

HOLD pulse width may be as narrow as 150 ns for all CLKIN frequencies

if CLKIN falls 95 ns after

HOLD falls. This ensures that the HOLD pulse will meet the minimum specification for thcf.

Parameter

Symbol

Min

Typ

Max

Unit

CLKIN Period

tclk

108

10,000

CLKIN Low Time

tclkl

37.5

CLKIN High Time

tclkh

37.5

Crystal Frequency

(Note 12)

fxtal

2.0

9.216

MHz

SLEEP Rising to Oscillator Stable

(Note 13)

RST Pulse Width

trst

150

RST to STBY falling

tdrrs

-100

RST Rising to STBY Rising

tcal

11,528,160

tclk

CH1/2 Edge to TRK1, TRK2 Rising

(Note 14)

tdrsh1

-80

CH1/2 Edge to TRK1, TRK2 Falling

(Note 14)

tdfsh4

68tclk+260 ns

HOLD to SSH Falling

(Note 15)

tdfsh2

-60

HOLD to TRK1, TRK2 Falling

(Note 15)

tdfsh1

66tclk

-68tclk+260 ns

HOLD to TRK1, TRK2, SSH Rising

(Note 15)

tdrsh

-120

HOLD Pulse Width

(Note 16)

thold

1tclk+20

63tclk

HOLD to CH1/2 Edge

(Note 15)

tdhlri

64tclk

HOLD Falling to CLKIN Falling

(Note 16)

thcf

1tclk+10

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