CS8420 datasheet(44/94 Pages) CIRRUS

44 / 94 page

DS245F4

CS8420

10.15 Receiver Error (10h) (Read Only)

This register contains the AES3 receiver and PLL status bits. Unmasked bits will go high on

occurrence of the error, and will stay high until the register is read. Reading the register resets

all bits to 0, unless the error source is still true. Bits that are masked off in the receiver error

mask register will always be 0 in this register. This register defaults to 00.

QCRC

Q-subcode data CRC error has occurred. Updated on Q-subcode block boundaries.

0 - No error

1 - Error

CCRC

Channel Status Block Cyclic Redundancy Check bit. Updated on CS block boundaries.

This bit is valid in Professional mode only.

0 - No error

1 - Error

UNLOCK

PLL lock status bit. Updated on CS block boundaries.

0 - PLL locked

1 - PLL out of lock

Received AES3 Validity bit status. Updated on sub-frame boundaries.

0 - Data is valid and is normally linear coded PCM audio

1 - Data is invalid, or may be valid compressed audio

CONF

Confidence bit. Updated on sub-frame boundaries.

0 - No error

1 - Confidence error. This indicates that the received data eye opening is less than

half a bit period, indicating a poor link that is not meeting specifications.

BIP

Bi-phase error bit. Updated on sub-frame boundaries.

0 - No error

1 - Bi-phase error. This indicates an error in the received bi-phase coding.

PAR

Parity bit. Updated on sub-frame boundaries.

0 - No error

1 - Parity error

76543210

QCRC

CCRC

UNLOCK

CONF

BIP

PAR

CS8420 Datasheet(PDF) 44 Page - Cirrus Logic

CS8420 Datasheet(HTML) 44 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94

Datasheet Download

Link URL