CS42432-DMZ datasheet(49/59 Pages) CIRRUS

49 / 59 page

DS673F1

CS42432

8.1.1

Passive Input Filter

The passive filter implementation shown in Figure 21 will attenuate any noise energy at 6.144 MHz but

will not provide optimum source impedance for the ADC modulators. Full analog performance will there-

fore not be realized using a passive filter. Figure 21 illustrates the unity gain, passive input filter solution.

In this topology the distortion performance is affected, but the dynamic range performance is not limited.

8.1.2

Passive Input Filter w/Attenuation

Some applications may require signal attenuation prior to the ADC. The full-scale input voltage will scale

with the analog power supply voltage. For VA = 5.0 V, the full-scale input voltage is approximately

2.8 Vpp, or 1 Vrms (most consumer audio line-level outputs range from 1.5 to 2 Vrms).

Figure 22 shows a passive input filter with 6 dB of signal attenuation. Due to the relatively high input im-

pedance on the analog inputs, the full distortion performance cannot be realized. Also, the resistor divider

circuit will determine the input impedance into the input filter. In the circuit shown in Figure 22, the input

impedance is approximately 5 k

Ω. By doubling the resistor values, the input impedance will increase to

10 k

Ω. However, in this case the distortion performance will drop due to the increase in series resistance

on the analog inputs.

2700 pF

C0G

μF

100 k

150

AIN1+,2+,3+,4+

AIN1-,2-,3-,4-

ADC1-2

4.7

μF

Figure 21. Passive Input Filter

2700 pF

C0G

μF

2.5 k

AIN1+,2+,3+,4+

AIN1-,2-,3-,4-

ADC1-2

4.7

μF

2.5 k

Figure 22. Passive Input Filter w/Attenuation

CS42432-DMZ Datasheet(PDF) 49 Page - Cirrus Logic

CS42432-DMZ Datasheet(HTML) 49 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59

Datasheet Download

Link URL