PM4351

Combined E1/T1/J1 Transceiver/Framer

COMET

PMC-1961230 (R3)

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

© Copyright PMC-Sierra, Inc. 2001

FEATURES

• Monolithic 3.3 V device that integrates

an E1/T1/J1 Framer and line driver for

shorthaul and longhaul applications.

• Software selectable between T1/J1

and E1 operation on a per device

basis.

• Provides fully programmable shorthaul

and longhaul pulse templates and line

build out.

• Meets or exceeds T1, J1, and E1

shorthaul and longhaul network access

specifications, which include:

ANSI T1.102, T1.403, T1.408, AT&T

TR 62411, ITU-T G.703 and G.823, as

well as the newer G.775 and

ETSI 300-011 specifications.

• Supports B8ZS, HDB3, and AMI line

codes.

• Provides receive clock recovery and

line performance monitoring.

• Provides on-board binary sequence

generators and detectors that can be

configured with various patterns for

error testing, including those

conforming to ITU-T 0.151.

• Provides transmit and receive jitter

attenuation.

• Provides three full-featured HDLC

controllers, each with 128-byte

transmit and receive FIFOs, enabling

dual compliance to the V5.1 and V5.2

interface standards.

• Supports an IEEE P1149.1 JTAG test

port.

• Automatically generates DS1

performance report messages to ANSI

T1.231 and other specifications.

, and MVIP PCM backplanes

supporting rates of 1.544 Mbit/s,

2.048 Mbit/s, 4.096 Mbit/s and

8.192 Mbit/s.

• Provides an 8-bit microprocessor bus

interface for configuration, control, and

status monitoring.

• Low power +3.3 V CMOS technology.

• Available in an 80-pin PQFP (14 mm

by 14 mm) and an 81-pin CABGA (9

mm by 9 mm) package.

• Provides a -40 °C to +85 °C industrial

temperature operating range.

RECEIVE

• Provides single-rail digital PCM and

signaling outputs for 1.544 Mbit/s,

2.048 Mbit/s, 4.096 Mbit/s, or

8.192 Mbit/s backplane buses.

• Guaranteed signal recovery of up to

-36 dB at 1024 kHz (E1) and 772 kHz

(T1/J1) under production test

conditions (VDD = 3.069 V, 25 °C)

using PIC-22 gauge cable emulation.

• Frames to a G.704 E1 signal.

• Frames to a JT-G704 J1 signal.

• Frames to a DSX/DS-1 signal in D4,

• Accommodates up to 0.4 UI peak-to-

peak, high frequency jitter as required

by AT&T TR 62411.

• Supports line and path performance

monitoring to AT&T and ANSI

specifications and ITU-T

recommendations.

• Detects both programmable in-band

loopback activate and deactivate code

sequences received in the DS1/E1

data stream.

TRANSMIT

• Supports transfer of transmitted PCM

and signaling data from 1.544 Mbit/s,

2.048 Mbit/s, 4.096 Mbit/s, or

8.192 Mbit/s backplane buses.

• Supports tristate line outputs.

• Generates DSX-1 T1 shorthaul- and

T1 longhaul-compatible pulses with

programmable pulse shape to AT&T

and ANSI specifications and ITU-T

recommendations.

• Generates G.703 E1 pulses.

• Detects violations of the ANSI T1.403

12.5% pulse density rule over a

moving 192-bit window.

• Allows insertion of in-band loopback

code sequences.

• Supports transmission of the Alarm

Indication Signal (AIS) or the yellow

alarm signal in all formats.

• Provides a FIFO for jitter attenuation in

the transmit path.

• Complies to all jitter attenuation, jitter

transfer and residual jitter

specifications required by AT&T TR

62411 and ETSI TBR12/13.

BLOCK DIAGRAM

RDLC #3

HDLC Receiver

TOPS

Timing Options

MPIF

Micro-

processor

Interface

D[7:0]

A[8:0]

RDB

WRB

CSB

ALE

RSTB

TDO

JTAG

Test

Access

Port

CSD

Clock Synthesis

and Distribution

RLPS

Receive

LIU

INTB

TDI

TCK

TMS

TRSTB

RX-ELST

Elastic

Store

TX-ELST

Elastic

Store

BTIF

Backplane

Transmit

Interface

FRMR

Frame

Alignment,

Alarm Extraction

FRAM

Framing

RAM

ALMI

Alarm

Integrator

BRIF

Bit-Oriented

Code Detector

IBCD

In-Band

Loopback Code

Detector

PMON

Performance

Monitor

Counters

PDVD

Pulse Density

Violation

Detector

RJAT

Receive

Digital Jitter

Attenuator

CDRC

Clock and Data

Recovery

XLPG

Transmit

LIU

FRMR

Frame

Alignment,

Alarm

Extraction

ALMI

Alarm

Integrator

IBCD

In-band

Loopback

Code

Detector

PMON

Performance

Monitor

Counters

XBOC

Bit-Oriented

Code

Generator

T1-XBAS/

E1-TRAN

Basic Transmitter:

Frame Generation,

Alarm Insertion,

Signaling Insertion,

Trunk Conditioning

RDLC #2

HDLC Receiver

RDLC #1

HDLC Receiver

RPSC

Per-DS0

Serial

Controller

PRGD

½ Pattern

Generator/

Detector

BRIF

Backplane

Receive

Interface

E1/T1-

SIGX

Signalling

Extractor

TDPR #3

HDLC Transmitter

TDPR #2

HDLC Transmitter

TDPR #1

HDLC Transmitter

TJAT

Transmit

Digital Jitter

Attenuator