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CY7C164 Datasheet(PDF) 3 Page - Cypress Semiconductor

Part # CY7C164
Description  16K x 4 Static RAM
PDF  9 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C164 Datasheet(HTML) 3 Page - Cypress Semiconductor

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CY7C164
CY7C166
Document #: 38-05025 Rev. *A
Page 3 of 9
AC Test Loads and Waveforms
Switching Characteristics Over the Operating Range[4]
CY7C164-15
CY7C166-15
CY7C164-25
CY7C166-25
Parameter
Description
Min.
Max.
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
15
25
ns
tAA
Address to Data Valid
15
25
ns
tOHA
Output Hold from Address Change
3
5
ns
tACE
CE LOW to Data Valid
15
25
ns
tDOE
OE LOW to Data Valid
7C166
10
12
ns
tLZOE
OE LOW to Low Z
7C166
3
3
ns
tHZOE
OE HIGH to High Z
7C166
8
10
ns
tLZCE
CE LOW to Low Z[5]
3
5
ns
tHZCE
CE HIGH to High Z[5, 6]
8
10
ns
tPU
CE LOW to Power-Up
0
0
ns
tPD
CE HIGH to Power-Down
15
20
ns
WRITE CYCLE[7]
tWC
Write Cycle Time
15
20
ns
tSCE
CE LOW to Write End
12
20
ns
tAW
Address Set-Up to Write End
12
20
ns
tHA
Address Hold from Write End
0
0
ns
tSA
Address Set-Up to Write Start
0
0
ns
tPWE
WE Pulse Width
12
15
ns
tSD
Data Set-Up to Write End
10
10
ns
tHD
Data Hold from Write End
0
0
ns
tLZWE
WE HIGH to Low Z[5]
5
5
ns
tHZWE
WE LOW to High Z[5, 6]
7
7
ns
Notes:
4. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
5. At any given temperature and voltage condition, tHZCE is less than tLZCE for any given device. These parameters are guaranteed by design and not 100% tested.
6. tHZCE and tHZWE are specified with CL = 5 pF as in part (b) in AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
7. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a
write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
3.0V
5V
OUTPUT
R1 481
Ω
R2
255
Ω
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
< 5ns
< 5 ns
5V
OUTPUT
R1 481
Ω
R2
255
Ω
5pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
OUTPUT
1.73V
Equivalent to:
THÉVENIN EQUIVALENT
ALL INPUT PULSES
C164–5
C164–6
167
Ω
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