Electronic Components Datasheet Search
  English  ▼

X  

Preview PDF HTML

TNETE2101APZ Datasheet(PDF) 6 Page - Texas Instruments

Part # TNETE2101APZ
Description  10BASE-T/100BASE-TX/100BASE-FX LOW-POWER PHYSICAL-LAYER INTERFACE
PDF  39 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TNETE2101APZ Datasheet(HTML) 6 Page - Texas Instruments

Back Button TNETE2101APZ Datasheet HTML 2Page - Texas Instruments TNETE2101APZ Datasheet HTML 3Page - Texas Instruments TNETE2101APZ Datasheet HTML 4Page - Texas Instruments TNETE2101APZ Datasheet HTML 5Page - Texas Instruments TNETE2101APZ Datasheet HTML 6Page - Texas Instruments TNETE2101APZ Datasheet HTML 7Page - Texas Instruments TNETE2101APZ Datasheet HTML 8Page - Texas Instruments TNETE2101APZ Datasheet HTML 9Page - Texas Instruments TNETE2101APZ Datasheet HTML 10Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 6 / 39 page
background image
TNETE2101
10BASE-T/100BASE-TX/100BASE-FX
LOW-POWER PHYSICAL-LAYER INTERFACE
SPWS032D – JANUARY 1997 – REVISED MARCH 1999
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
Terminal Functions (Continued)
MII interface (continued)
TERMINAL
TYPE†
I/O
DESCRIPTION
NAME
NO.
TYPE†
I/O
DESCRIPTION
MTXEN
58
5-V TTL
I
Transmit enable. MTXEN indicates valid transmit data on MTXD0–MTXD3. MTXEN is
synchronous to MTCLK.
MTXER
57
5-V TTL
I
Transmit error. MTXER allows coding errors to be propagated across the MII. MTXER is
synchronous to MTCLK.
† 5-V TTL terminals are 5-V tolerant if VDD5 is connected to 5 V.
miscellaneous
TERMINAL
TYPE‡
I/O
DESCRIPTION
NAME
NO.
TYPE‡
I/O
DESCRIPTION
SLINK
(CDEVSEL3)
39
TTL
I/O
Link status. When asserted high, SLINK indicates that a good link has been established with
the link partner. When autonegotiation is enabled, SLINK also indicates that the CSPEED and
CDUPLEX terminals are being driven with the negotiated speed and duplex configuration. The
value of SLINK is latched on the rising edge of MRST for use as CDEVSEL3, bit 3, of the MII
device-select address.
XTAL1
11
A
I
Clock input. XTAL1 is the main 20-MHz reference clock input for the TNETE2101. A 20-MHz
clock oscillator can be connected to XTAL1, or a crystal with a capacitor network can be
connected across XTAL1 and XTAL2.
XTAL2
12
A
O
Output for external crystal circuit. See XTAL1.
‡ A = analog
network interface
TERMINAL
TYPE‡
I/O
DESCRIPTION
NAME
NO.
TYPE‡
I/O
DESCRIPTION
ACT
85
A
O
Center tap. ACT is the connection to the primary center tap of the transmit transformer.
ARCVP
ARCVN
91
92
A
I
Receive pair. ARCVP and ARCVN are the differential line inputs to the device from the transformer
and termination components.
AXMTP
AXMTN
87
88
A
O
Transmit pair. AXMTN and AXMTP are the differential line outputs from the device to the transformer
and termination components.
‡ A = analog
no connection
TERMINAL
DESCRIPTION
NAME
NO.
DESCRIPTION
NC
15, 17, 64, 74, 94, 95, 97, 98
No connection (no external connection allowed).



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com