4

1222F—3/13/07

ICSSSTUB32872A

Advance Information

Ball Assignment

Signal Group

Signal Name

Type

Description

Ungated inputs DCKE0, DCKE1,

DODT0, DODT1

SSTL_18

DRAM function pins not associated with Chip Select.

Chip Select

gated inputs

D0 ... D21

SSTL_18

DRAM inputs, re-driven only when Chip Select is LOW.

Chip Select

inputs

DCS0 , DCS1

SSTL_18

DRAM Chip Select signals. These pins initiate DRAM

address/command decodes, and as such at least one will be

low when a valid address/command is present. The register

can be programmed to re-drive all D-inputs

Re-driven

outputs

Q0...Q21,

QCS0-1,

QCKE0-1,

QODT0-1

SSTL_18

Outputs of the register, valid after the specified clock count

and immediately following a rising edge of the clock.

Parity input

PARIN

SSTL_18

Input parity is received on pin PARIN and should maintain

odd parity across the D0...D20 inputs, at the rising edge of the

clock.

Parity error

output

PTYERR

Open drain

When LOW, this output indicates that a parity error was

identified associated with the address and/or command inputs.

PTYERR will be active for two clock cycles, and delayed by

an additional clock cycle for compatibility with final parity

out timing on the industry-standard DDR-II register with

parity (in JEDEC definition).

Clock inputs

CK, CK

SSTL_18

Differential master clock input pair to the register. The

register operation is triggered by a rising edge on the positive

clock input (CK).

Miscellaneous

inputs

RESET

1.8 V

LVCMOS

Asynchronous reset input. When LOW, it causes a reset of the

internal latches, thereby forcing the outputs LOW. RESET

also resets the PTYERR signal.

VREF

0.9 V nominal Input reference voltage for the SSTL_18 inputs. Two pins

(internally tied together) are used for increased reliability.

when at least

one Chip Slect input is LOW.