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PIMXRT204VCFP4A Datasheet(PDF) 56 Page - NXP Semiconductors

Part # PIMXRT204VCFP4A
Description  i.MX RT1060 Crossover Processors for Consumer Products
PDF  119 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

PIMXRT204VCFP4A Datasheet(HTML) 56 Page - NXP Semiconductors

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i.MX RT1060 Crossover Processors for Consumer Products, Rev. 4, 04/2024
56
NXP Semiconductors
Electrical Characteristics
NOTE
TCSS and TCSH are configured by the FlexSPIn_FLSHAxCR1
register, the default values are shown above. See more details in the i.MX
RT1060 Reference Manual (IMXRT1060RM).
Figure 25. FlexSPI output timing in SDR mode
4.5.2.2.2
SDR mode
NOTE
TCSS and TCSH are configured by the FlexSPIn_FLSHAxCR1
register, the default values are shown above. See more details in the i.MX
RT1060 Reference Manual (IMXRT1060RM).
TCSS
Chip select output setup time
3 x TCK - 1
—
ns
TCSH
Chip select output hold time
3 x TCK + 2
—
ns
1 The actual maximum frequency supported is limited by the FlexSPIn_MCR0[RXCLKSRC] configuration used. Please refer to the FlexSPI SDR input timing
specifications.
Table 46. FlexSPI output timing in SDR mode
Symbol
Parameter
Min
Max
Unit
Frequency of operation1
1 The actual maximum frequency supported is limited by the FlexSPIn_MCR0[RXCLKSRC] configuration used. Please refer to the FlexSPI SDR input timing
specifications.
—
166
MHz
Tck
SCK clock period (FlexSPIn_MCR0[RXCLKSRC] = 0x0)
6.0
—
ns
TDVO
Output data valid time
—
2.2
ns
TDHO
Output data hold time
0.8
—
ns
TCSS
Chip select output setup time
3 x TCK /2 - 0.7 —
ns
TCSH
Chip select output hold time
3 x TCK /2 + 0.8 —
ns
Table 45. FlexSPI output timing in SDR mode (continued)
Symbol
Parameter
Min
Max
Unit
T CSS
T CK
TCSH
TDVO
TDHO
TDVO
TDHO
SCK
CS
SIO[0:7]



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