PIMXRT804VCFP4A datasheet(15/119 Pages) NXP

15 / 119 page

Modules List

i.MX RT1060 Crossover Processors for Consumer Products, Rev. 4, 04/2024

NXP Semiconductors

FLEXCAN (FD)

Flexible Controller Area

Network

Connectivity

Peripherals

The CAN with Flexible Data-Rate protocol and the CAN

2.0 version B protocol supports both standard and

extended message frames, both of them have long

payloads up to 64 bytes transferred at faster rates up to

8 Mbps.

FlexIO1

FlexIO2

FlexIO3

Flexible Input/output

Connectivity and

Communications

The FlexIO is capable of supporting a wide range of

protocols including, but not limited to: UART, I2C, SPI,

I2S, camera interface, display interface, PWM

waveform generation, etc. The module can remain

functional when the chip is in a low power mode

provided the clock it is using remain active.

FlexPWM1

FlexPWM2

FlexPWM3

FlexPWM4

Pulse Width Modulation

Timer Peripherals The pulse-width modulator (PWM) contains four PWM

sub-modules, each of which is set up to control a single

half-bridge power stage. Fault channel support is

provided. The PWM module can generate various

switching patterns, including highly sophisticated

waveforms.

FlexRAM

RAM

Memories

The i.MX RT1060 has 1 MB of on-chip RAM which

could be flexible allocated to I-TCM, D-TCM, and

on-chip RAM (OCRAM) in a 32 KB granularity. The

FlexRAM is the manager of the on-chip RAM array.

Major functions of this blocks are: interfacing to I-TCM

and D-TCM of Arm core and OCRAM controller;

dynamic RAM arrays allocation for I-TCM, D-TCM, and

OCRAM.

FlexSPI1

FlexSPI2

Quad Serial Peripheral

Interface

Connectivity and

Communications

FlexSPI acts as an interface to one or two external

serial flash devices, each with up to four bidirectional

data lines.

GPIO1

GPIO2

GPIO3

GPIO4

GPIO5

General Purpose I/O

Modules

System Control

Peripherals

Used for general purpose input/output to external ICs.

Each GPIO module supports up to 32 bits of I/O.

GPT1

GPT2

General Purpose Timer

Timer Peripherals Each GPT is a 32-bit “free-running” or “set and forget”

mode timer with programmable prescaler and compare

and capture register. A timer counter value can be

captured using an external event and can be configured

to trigger a capture event on either the leading or trailing

edges of an input pulse. When the timer is configured to

operate in “set and forget” mode, it is capable of

providing precise interrupts at regular intervals with

minimal processor intervention. The counter has output

compare logic to provide the status and interrupt at

comparison. This timer can be configured to run either

on an external clock or on an internal clock.

Table 2. i.MX RT1060 modules list (continued)

Block Mnemonic

Block Name

Subsystem

Brief Description

PIMXRT804VCFP4A Datasheet(PDF) 15 Page - NXP Semiconductors

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