PM5381

Preliminary

PMC-Sierra,Inc.

SATURN® User Network Interface for 2488 Mbit/s

S/UNI®-2488

PMC-2000453 (p2)

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

© Copyright PMC-Sierra, Inc. 2000

FEATURES

• Single chip ATM and POS User-

Network Interface operating at 2488.32

Mbit/s.

• Implements the ATM Forum User

Network Interface Specification and

the ATM physical layer for Broadband

ISDN according to CCITT

Recommendation I.432.

• Implements the Point-to-Point Protocol

(PPP) over SONET/SDH specification

according to RFC 2615(1619)/1662 of

the PPP Working Group of the Internet

Engineering Task Force (IETF).

• Processes bit-serial 2488.32 Mbit/s

STS-48 (STM-16-16c) data streams

with on-chip clock and data recovery

and clock synthesis.

• Complies with Bellcore GR-253-CORE

jitter tolerance, jitter transfer and

intrinsic jitter criteria.

• Provides termination for SONET

Section, Line and Path overhead or

SDH Regenerator Section, Multiplexer

Section and High Order Path

overhead.

• Provides UTOPIA Level 3 32-bit wide

System Interface (clocked up to

104 MHz) with parity support for ATM

applications.

• Provides SATURN POS-PHY

Level 3™ 32-bit System Interface

(clocked up to 104 MHz) for Packet

over SONET (POS), or ATM

applications.

• Supports line loopback from the line

side receive stream to the transmit

stream and diagnostic loopback from

the line side transmit stream to the line

side receive stream interface.

• Provides support for automatic

protection switching including a bi-

directional 4-bit LVDS 777.76 MHz

port.

• Provides a standard five signal IEEE

1149.1 JTAG test port for boundary

scan board test purposes.

• Provides a generic 16-bit

microprocessor bus interface for

configuration, control, and status

monitoring.

PGMRCLK

POSL3_UL3B

SD

RXD+/-

OOF

RCLK

TCLK

PGMTCLK

TXD+/-

REFCLK+/-

Microprocessor

Interface

JTAG

Rx Line

Interface

Tx Line

Interface

Rx Path O/H

Processor

Tx Path

O/H

Processor

ATM/HDLC

Processor

UTOPIA

Level 3 /

POS Level

3 Transmit

Interface

FIFO

RX

Transport

O/H

Processor

Rx APS Sync

Extractor &

Bit Error

Monitor

Section

Trace

Processor

Rx LVDS

Interface

Rx APS

Rx Telecom

Aligner

Tx

Transport

O/H

Processor

Section

Trace

Processor

Tx LVDS

Interface

Path

Trace

Processor

ATM/HDLC

Processor

UTOPIA

Level 3 /

POS Level

3 Receive

Interface

FIFO

SALM

RALM

SONET/SDH

Alarm

Reporting

Controller

Tx APS

Path

Trace

Processor

PRBS

Generator/

Monitor

TENB

TCA/PTPA

TSOC/TSOP

TPRTY

TFCLK

TDAT[31:0]

TERR

TEOP

TMOD[1:0]

RENB

RCA/RVAL

RSOC/RSOP

RPRTY

RFCLK

RDAT[31:0]

RSX

RERR

REOP

RMOD[1:0]

Analog

C0 C1

C2 C3

RES_RESK

ATP[3:0]

BLOCK DIAGRAM