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SATURN® User Network Interface for 9.953 Gbit/s

S/UNI®-9953-POS

PMC-2010908 (A1)

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

 Copyright PMC-Sierra, Inc. 2001

GENERAL DESCRIPTION

• The S/UNI-9953-POS is a single chip

ATM, POS User-Network Interface

operating at 9953.28 Mbit/s. The S/UNI

9953-POS is intended for use in OC-

192c and high-density OC-48c

POS/ATM applications.

FEATURES

• Supports framing, scrambling/

descrambling and pointer processing

for the following:

•

STS-192c (STM-64-64c).

•

4 x STS-48c (4 x STM-16-16c).

•

STS-192 (STM-64) channelized

down to STS-48c (STM-16c).

• Supports alarm signal

insertion/detection, B1/2/3 processing

and insertion/termination of SONET

Section/Line/Path overhead bytes (or

SDH equivalents).

• Provides ATM and POS payload

processing for:

•

STS-192c (STM-64-64c)

•

4 x STS-48c (4 x STM-16-16c).

•

STS-192 (STM-64) channelized

down to STS-48c (STM-16c).

INTERFACES

• Provides SATURN® POS-PHY™

Level 4 16-bit LVDS System-side

Interface (clocked at 700 MHz

nominal).

• Directly connects to optics via 16 bit by

622 MHz OIF SFI-4 (OIF99.102) line-

side interface.

POS/ATM

• Implements the ATM Forum User

Network Interface Specification and

the ATM physical layer for Broadband

ISDN according to CCITT

Recommendation I.432.

• Implements the Point-to-Point Protocol

(PPP) over SONET/SDH specification

according to RFC 2615(1619)/1662 of

the PPP Working Group of the Internet

Engineering Task Force (IETF).

GENERAL

• Provides internal FIFOs (16 KB

ingress, 20 KB egress) to

accommodate system latencies.

• Provides line-side and system-side

loopbacks for system level diagnostic

capability.

• Provides support for automatic

protection switching (APS) via two 16-

bit LVDS 777.76 MHz ports.

• Provides a generic 16-bit

microprocessor bus interface for

configuration, control and status

monitoring.

• Standard 5 signal P1149.1 JTAG test

port.

Rx

Transport

O/H

Processor

APS

Rx Path

O/H

Processor

Rx Payload

Aligner

Rx Cell/

Frame

Processor

Rx SONET

BER

Monitor

Tx

Transport

O/H

Processor

Tx High-

Order Path

O/H

Processor

APS

LVDS I/F

TXCLK_SRC+/-

RXCLK+/-

RXDATA+/-

TXDATA +/-

TXCLK+/-

Microprocessor

JTAG

POS-PHY

Level 4

Interface

Ingress

Flexible

FIFO

POS-PHY

Level 4

Interface

Egress

Flexible

FIFO

PL4 REF +/-

RDCLK +/-

RDAT+/-

RSCLK

RSTAT

TDCLK +/-

TDAT+/-

TSCLK

TSTAT

RCTL+/-

TCTL+/-

SFI-4

Rx

Interface

SFI-4

Tx

Interface

LVDS I/F

Tx Cell/

Frame

Processor

BLOCK DIAGRAM