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PM6341 Datasheet(PDF) 1 Page - PMC-Sierra, Inc

Part # PM6341
Description  E1 TRANSCEIVER
PDF  2 Pages
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Manufacturer  PMC [PMC-Sierra, Inc]
Direct Link  http://www.pmc-sierra.com
Logo PMC - PMC-Sierra, Inc

PM6341 Datasheet(HTML) 1 Page - PMC-Sierra, Inc

  PM6341 Datasheet HTML 1Page - PMC-Sierra, Inc PM6341 Datasheet HTML 2Page - PMC-Sierra, Inc  
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PMC-920109(R6)
E1 TRANSCEIVER
© 1998 PMC-Sierra, Inc. March, 1998
PM6341
Summary Information
E1XC
BLOCK DIAGRAM
FEATURES
• Monolithic single chip device which
integrates a full-featured E1 framer
with on-chip analog line interface.
• Provides frame synchronization and
frame generation for a G.704/G.706
2.048 Mbit/s signal with capability to
support the optional signalling and
CRC multiframes.
• Supports HDB3 or AMI line coding
and accepts gapped data streams to
support higher rate demultiplexing.
• Supports both 75 Ohm and 120 Ohm
G.703 line interfaces.
• Provides Channel Associated
Signalling extraction/insertion,
programmable idle code substitution,
digital milliwatt code substitution,
data inversion and up to 3
multiframes of signalling debounce
on a per channel basis.
• Optionally extracts/inserts the
datalink from/to timeslot 16 to
receive/transmit Common Channel
Signalling.
• Pin compatible with the PM4341A
T1XC T1 Transceiver.
• Software compatible with the
PM6344 EQUAD E1 Framer, and
PM6388 EOCTL E1 Framer.
• Provides an 8-bit microprocessor bus
interface for configuration, control
and status monitoring.
• Low-power 5V CMOS technology.
• Available in a high density 80-pin (14
by 14mm) PQFP or in a 68-pin PLCC
package.
• E1 & E3 Multiplexers
• Digital Loop Carriers
• E1 Frame Relay Interfaces
• E1 ATM UNI Interfaces
• E1 Channel Service Units (CSUs)
and Data Service Units (DSUs)
• Digital Access and Cross-Connect
Systems (DACS) and Electronic
Digital Cross-Connect Systems
(EDSX)
• SDH Add/Drop Multiplexers (ADM)
• ISDN Primary Rate Interfaces (PRI)
• Digital Private Branch Exchanges
(PBX)
• E1 & E3 Test Equipment
APPLICATIONS
RECEIVE SECTION
• Provides indications of loss of
signal, loss of frame alignment
(OOF), loss of signalling multiframe
alignment and loss of CRC
multiframe alignment.
• Declares red and AIS alarms using
Q.516 recommended integration
periods
• Supports line and path performance
monitoring according to ITU-T
recommendations. Accumulators
are provided for CRC-4 errors, Far
End Block Errors, Frame sync errors,
and Line Code Violations.
• Provides an integral HDLC/LAPD
interface which may be used for
terminating a CCS or National Bits
datalink.
• Provides a two frame elastic store for
jitter and wander attenuation.
• Provides programmable trunk
conditioning on a per channel basis.
TRANSMIT SECTION
• Supports transmission of AIS,
timeslot 16 AIS, remote alarm signal
or remote multiframe alarm signal.
• Provides an integral HDLC/LAPD
interface which may be used for
generating a CCS or National Bits
datalink.
• Provides an integrated digital phase
locked loop for generation of a low
jitter transmit clock.
• Provides a FIFO buffer for jitter
attenuation and rate conversion.
• Provides programmable trunk
conditioning which forces trouble
code substitution and signalling
conditioning on a per channel basis.
XCLK/VCLK
BRFPI
BRC LK
BRPCM /BR DP
BRSIG /BR DN
BRFPO
RCLKO
RFP
R DPCM/RPCM
RDLCLK/
RDLEO M
RDLSIG /
RDLINT
RCLKI
RDP/RDD/
SDP
RDN/RLCV/
SDN
R AS
REF
RRC
RFDL
HDLC
RECEIVER
CDRC
CLO CK AN D
DATA
RECOVERY
PM O N
PER F
MO NITOR
COUNTERS
SIG X
SIG NALLIN G
EXTRACT,
TRU NK
CONDITION
ELST
ELASTIC
STO RE
BR IF
BAC K-
PLANE
RECEIVE
INTER-
FAC E
RS L C
ANALO G
PULSE
SLIC ER
TDP/TD D
TCLKO
TDN /TFLG
TCLKI
TAN
TAP
BTPCM /BTDP
BTC LK
BTSIG/BTD N
TDLSIG /
TDLINT
TDLCLK/
TDLUD R
INTB
D(7-0)
A(7-0)
RDB
WRB
C SB
ALE
RSTB
BTF P
TC
XFD L
HDLC
TRANS-
MITTER
TR A N
TRANSMITTER:
FRAME GENERATIO N,
ALARM IN SER TIO N,
TRUNK CONDITION ING
LINE CODING
PCSC
PER-CHAN
CONTR:
SIG NAL,
IDLE CONT
DTIF
DIG ITAL
TRANSMIT
INTERFAC E
MP IF
MIC RO -
PRO CESSOR
INTERFAC E
INTERN AL
BUS
RE C E IV E R
TR A N S M IT T E R
XBO C
BIT-
OR IEN TED
CODE
TRANS
DR IF
DIG ITAL
RECEIVE
INTERFAC E
RB OC
BIT
OR IEN TED
CODE
DETECTO R
FR M R
FR AMER:
FRAM E
ALIG NM EN T,
ALARM
DETECTIO N
BTIF
BAC K-
PLANE
TRANS-
MIT
INTER-
FAC E
TO P S
TIM ING OPTIO NS
DJAT
D IG ITAL JITTER
ATTEN UATOR
XP L S
ANALO G
PULSE
GENERATOR


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