PM73123

8 Link CES/DBCES AAL1 SAR

AAL1gator™-8

PMC-1991272 (r2)

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

 Copyright PMC-Sierra, Inc. 2001

FEATURES

• Supports eight structured/unstructured

T1, E1 links or one unstructured DS3,

E3 or STS-1/STM-0 link over an AAL1

CBR ATM network.

• Compliant with ATM Forum's CES (AF-

VTOA-0078), and ITU-T I.363.1.

• Supports up to 256 VCs.

• Supports n x 64 (consecutive

channels) and m x 64 (non-

consecutive channels) structured data

format with channel associated

signaling (CAS) support.

• Internal E1/T1 clock synthesizers

provided for each line which can be

controlled via internal synchronous

residual time stamp (SRTS) or an

internal programmable weighted

moving average adaptive clocking

algorithm in unstructured mode. Clock

synthesizers can also be controlled

externally to provide customization of

SRTS or adaptive clocking methods.

• Provides transparent transmission of

CCS and CAS and termination of CAS

signaling.

• Compliant with ATM Forum's Dynamic

Bandwidth Circuit Emulation Service

(DBCES) AF-VTOA-0085. Supports

idle channel detection via processor

intervention, CAS signaling, or data

pattern detection. Provides idle

channel indication on a per channel

basis.

• Supports AAL0 mode, selectable on a

per VC basis.

• Provides transmit and receive buffers

which can be used for OAM cells as

well as any other user-generated cells

such as AAL5 cells for ATM signaling.

LINE INTERFACE

• Supports the following flexible line

interfaces:

•

Eight individual T1 or E1 lines.

•

Two H-MVIP lines at 8 MHz.

•

One unstructured DS3, E3 or STS-

1/STM-0 line.

• Provides lineside loopback support on

a per channel basis.

UTOPIA INTERFACE

• Supports 52 MHz, 8/16-bit Level 2,

Multi-Phy Mode (MPHY) with parity,

8/16-bit Level 1, SPHY and 8-bit

Level 1, ATM Master modes.

• Provides an optional 8/16-bit Any-

PHY™ slave interface.

• Provides a three cell FIFO for UTOPIA

loopback support on a per VC basis or

a global basis.

TRANSMIT SECTION

• Provides individually enabled per-VC

data and signaling conditioning in the

transmit cell direction and per DS0

data and signaling conditioning in the

transmit line direction. Includes DS3

AIS conditioning support in both

directions.

• Provides per-VC configuration of time

slots allocated, CAS support, partial

cell size, data and signaling

conditioning, ATM Cell header

definition.

• Generates AAL1 sequence numbers,

pointers and SRTS values in

accordance with ITU-T I.363.1.

Multicast connections are supported.

• Provides a patented frame based

calendar queue service algorithm with

anti-clumping add-queue mechanism

that produces minimal CDV. In

unstructured mode, uses non-frame

based scheduling to optimize CDV.

BLOCK DIAGRAM

UTOPIA

Interface

8

TATM_DATA[15:0]

TATM_PAR

TATM_ENB

TATM_SOC

TATM_CLAV

TATM_CLK

RPHY_ADD[4:0]

RATM_DATA[15:0]

RATM_PAR

RATM_ENB

RATM_SOC

RATM_CLAV

RATM_CLK

TPHY_ADD[4:0]

A1SP

8

Line Interface

JTAG

RAM

Interface

Processor Interface

External Clock

Interface

Clock

MUX

8

H-MVIP

8

F0B

TL_SIG[7:0]

TL_DATA[7:0]

TL_SYNC[7:0]

RL_SIG[7:0]

RL_DATA[7:0]

RL_SYNC[7:0]

LINE_MODE

8

Direct

Mode

8

RSTB

SCAN_ENB

SCAN_MODEB