CY7C656xx
Document #: 38-08037 Rev. *H
Page 2 of 24
Introduction
EZ-USB HX2LP™ is Cypress’ next generation family of high
performance, low power USB 2.0 hub controllers. HX2LP is an
ultra low power single chip USB 2.0 hub controller with
integrated upstream and downstream transceivers, a USB
Serial Interface Engine (SIE), USB Hub Control and Repeater
logic, and Transaction Translator (TT) logic. Cypress has also
integrated many of the external passive components, such as
pull up and pull down resistors, reducing the overall bill of
materials required to implement a hub design. The HX2LP
portfolio consists of:
1. CY7C65630: 4-port/single transaction translator
This device option is for ultra low power applications that
require four downstream ports. All four ports share a single
transaction translator. The CY7C65630 is available in a 56
QFN
and
is
also
pin-for-pin
compatible
with
the
CY7C65640.
2. CY7C65620:
This device option is for a 2-port bus powered application.
Both ports share a single transaction translator. The
CY7C65620 is available in a 56 QFN.
All device options are supported by Cypress’ world class
reference design kits, which include board schematics, bill of
materials, Gerber files, Orcad files, and thorough design
documentation.
USB Serial Interface Engine
The Serial Interface Engine (SIE) allows the CY7C656xx to
communicate with the USB host. The SIE handles the
following USB activity independently of the Hub Control Block.
• Bit stuffing/unstuffing
• Checksum generation/checking
• TOKEN type identification
• Address checking.
Routing Logic
Hub Repeater
USB Upstream Port
USB 2.0 PHY
PLL
Serial
Interface
Engine
High-Speed
USB Control Logic
SPI Communication
Block
USB Downstream Port 1
USB 2.0
PHY
Port Power
Control
Port
Status
USB Downstream Port 2
USB 2.0
PHY
Port Power
Control
Port
Status
USB Downstream Port 3
USB 2.0
PHY
Port Power
Control
Port
Status
USB Downstream Port 4
USB 2.0
PHY
Port Power
Control
Port
Status
SPI_SCK
SPI_CS
SPI_SD
D+
D-
PWR#[4]
OVR#[4]
LED
D+
D- PWR#[3]
OVR#[3]
LED
D+
D-
PWR#[2]
OVR#[2]
LED
D+
D- PWR#[1]
OVR#[1]
LED
Transaction Translator (X1)
TT RAM
D+
D -
24 MHz
Crystal
Block Diagram
CY7C65620
[+] Feedback
[+] Feedback
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
