CY29948ACT datasheet(2/8 Pages) CYPRESS

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CY29948

Document #: 38-07288 Rev. *C

Page 2 of 8

Output Enable/Disable

The CY29948 features a control input to enable or disable the

outputs. This data is latched on the falling edge of the input

clock. When SYNC_OE is asserted LOW, the outputs are

disabled in a LOW state. When SYNC_OE is set HIGH, the

outputs are enabled as shown in Figure 1.

Note:

1. PD = Internal pull-down, PU = Internal pull-up.

Pin Description[1]

Name

PWR

I/O

Description

PECL_CLK

I, PU

PECL Input Clock

PECL_CLK#

I, PD

PECL Input Clock

2TCLK

I, PU

External Reference/Test Clock Input

9, 11, 13, 15,

17, 19, 21, 23,

25, 27, 29, 31

Q(11:0)

VDDC

Clock Outputs

TCLK_SEL

I, PU

Clock Select Input. When LOW, PECL clock is selected. When HIGH

TCLK is selected.

SYNC_OE

I, PU

Output Enable Input. When asserted HIGH, the outputs are enabled.

When set LOW the outputs are disabled in a LOW state.

TS#

I, PU

Three-state Control Input. When asserted LOW, the output buffers

are three-stated. When set HIGH, the output buffers are enabled.

10, 14, 18, 22,

26, 30

VDDC

2.5V or 3.3V Power Supply for Output Clock Buffers

7VDD

2.5V or 3.3V Power Supply

8, 12, 16, 20,

24, 28, 32

VSS

Common Ground

TCLK

SYNC_OE

Figure 1. SYNC_OE Timing Diagram

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