AD7767 datasheet(15/24 Pages) AD

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AD7767

Rev. 0 | Page 15 of 24

THEORY OF OPERATION

The AD7767/AD7767-1/AD7767-2 operate using a fully

differential analog input applied to a successive approximation

(SAR) core. The output of the oversampled SAR is filtered using

a linear phase digital FIR filter. The fully filtered data is output

in a serial format, with the MSB being clocked out first.

AD7767/AD7767-1/AD7767-2 TRANSFER

FUNCTION

The conversion results of the AD7767/AD7767-1/AD7767-2 are

output in a twos complement, 24-bit serial format. The fully

differential inputs VIN+ and VIN− are scaled by the AD7767/

AD7767-1/AD7767-2 relative to the reference voltage input

(VREF+), as shown in Figure 28.

100...000

100...001

111...110

111...111

000...000

000...001

000...010

011...110

011...111

24 BITS

TWOS

COMPLEMENT

VIN+ = 0V

VIN+ = VREF – 1LSB

VIN– = VREF – 1LSB

VIN– = 0V

VIN+ =

VREF

VIN– =

VREF

Figure 28. AD7767/AD7767-1/AD7767-2 Transfer Function

CONVERTER OPERATION

Internally, the input waveform applied to the SAR core is

converted and an equivalent digital word is output to the digital

filter at a rate equal to MCLK. By employing oversampling, the

quantization noise of the converter is spread across a wide

bandwidth from 0 to fMCLK. This means that the noise energy

contained in the signal band of interest is reduced (see

Figure 29).

QUANTIZATION NOISE

BAND OF INTEREST

fMCLK/2

Figure 29. Quantization Noise

DIGITAL FILTER CUTOFF FREQUENCY

fMCLK/2

BAND OF INTEREST

Figure 30. Digital Filter Cutoff Frequency

The digital filtering that follows the converter output acts to

remove the out-of-band quantization noise (see Figure 30). This

also has the effect of reducing the data rate from fMCLK at the

input of the filter to fMCLK/8, fMCLK/16, or fMCLK/32 at the digital

output, depending on which model of the device is being used.

The digital filter consists of three separate filter blocks. Figure 31

shows the three constituent blocks of the filter. The order of

decimation of the first filter block is set as 2, 4, or 8. The

remaining sections both operate in decimate by 2.

STAGE 1

STAGE 2

DIGITAL FILTER

STAGE 3

SINC FILTER

FIR FILTER

DEC × (2 × n)

DEC × 2

DATA

STREAM

SDO

Figure 31. FIR Filter Stages

(n = 1 for AD7767, n = 2 for AD7767-1, n = 4 for AD7767-2)

Table 6 shows the three available models of the AD7767, listing

the change in output data rate relative to the order of decimation

rate implemented. This brings into focus the trade-off that

exists between extra filtering and reduction in bandwidth,

whereby using a filter option with a larger decimation rate

increases the noise performance while decreasing the usable

input bandwidth.

Table 6. AD7767 Models

Model

Decimation Rate

Output Data Rate (ODR)

AD7767

128 kHz

AD7767-1

64 kHz

AD7767-2

32 kHz

Note that the output data rates shown in Table 6 are realized

when using the maximum MCLK input frequency of 1.024 MHz.

The output data rate scales linearly with the MCLK frequency,

as does the digital power dissipated in the device.

The settling time of the filter implemented on the AD7767,

AD7767-1, and AD7767-2 is related to the length of the filter

employed. The response of the filter in the time domain sets the

filter settling time. Table 7 shows the filter settling times of the

AD7767/AD7767-1/AD7767-2.

The frequency responses of the digital filters on the AD7767,

AD7767-1, and AD7767-2 are shown in Figure 32, Figure 33,

and Figure 34, respectively. At the Nyquist frequency (output

data rate/2), the digital filter provides 6 dB of attenuation. In each

case, the filter provides stop-band attenuation of 100 dB and

pass-band ripple of ±0.005 dB.

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