LB11873

No.A0081-13/14

10. Phase lock signal

(1) Phase lock range

Since this IC does not have a speed system counter, the speed error range in the phase locked state cannot be

determined by the IC characteristics alone. (This is because the range is affected by the acceleration with changes in the

FG frequency.) If it is necessary to stipulate this in conjunction with a motor, it will be necessary to measure the range

with the actual motor state. Since speed errors occur easily in states where the FG acceleration is large, it is thought that

the lock pull-in time at startup and the unlock time due to clock switching will be the cases where the speed error is the

largest.

(2) Phase lock signal mask function

It is possible to assure that the lock signal is output in stable states by masking the short-term low levels due to hunting

during lock pull-in. Note, however, that the lock signal output will be delayed by the amount of the mask time.

The mask time is set by the capacitor connected between the CLD pin and ground.

Mask time (s)

≈ 6.5 × 0.98 × CCSD (μF)

When a 0.033µF capacitor is used, the mask time will be about 210ms. If full masking is required, the mask time must

be set with an adequate margin.

11. Initial reset

To apply an initial reset to the logic circuit, the IC goes to the reset state until the CSD pin voltage changes from 0V to

about 0.63V. After the reset is cleared, drive will start. The reset time can be calculated quite closely with the following

equation.

Reset time (s)

≈ 0.13 × CCSD (μF)

A reset time of over 100µs is required.

12. Power supply stabilization

Since this IC is used in switching drive applications with large output currents, the power supply line is easily

disrupted.

Therefore it is necessary to connect an adequately large capacitor between the VCC pin and ground.

The capacitor ground side is connected to the GND2 pin, which is the power system ground, and must be connected as

close as possible to the pin.

If the capacitor (an electrolytic capacitor) cannot be connected close to the pin, a ceramic capacitor of about 0.1µF must

be connected close to the pin.

If reverse control mode (torque braking) is selected for braking, since there will be states where the current returns to

the power supply, the power supply line level will be especially subject to disruption. Since the power supply line is

most easily disrupted during lock pull-in at high speeds, designers must analyze this case carefully and select an

adequately large capacitor.

Since the power supply line is particularly susceptible to disruption if a diode is inserted in the power supply line to

prevent destruction of the IC by reverse connection, an even larger capacitor must be selected in this case.

13. VREG stabilization

Connect a capacitor with a value over 0.1µF to stabilize the VREG voltage, which is the IC's control circuit power

supply. This capacitor's ground side must be connected as close as possible to the IC's control block ground (the GND1

pin).

14. Error amplifier system components

The external components for the error amplifier block must be located as close as possible to the IC to minimize the

influence of noise. These components must also be located as far from the motor as possible.

15. FRAME pin

An electrolytic capacitor must be connected between the FRAME pin and GND2 with the capacitor's ground side is

connected to GND2.