LB11876

No.8317-13/15

LB11876 Overview

1. Speed control circuit

Since the LB11876 adopts PLL speed control, it provides precise, low-jitter, and stable motor operation. This PLL

circuit compares the falling edge of the CLK signal with the FG signal (the falling edges of the FGIN+ or FGS output)

and controls motor operation based on the difference.

The FG servo frequency during this control operation is controlled by the frequency given by the following formula

which is based on the divisor selected by the clock input frequency (fCLK) and the CLKSEL pin.

fFG (servo) = fCLK ÷ <divisor>

2. Output drive circuit

To minimize the power loss in the output, the LB11876 adopts direct PWM drive. The output transistors, which are

external, are always saturated when on and the motor drive power is adjusted by changing the duty with which the

output is on.

The PWM switching is performed with the UH, VH, and WH outputs. Either high side or low side switching can be

selected by the way the output transistors are connected.

3. Current limiter circuit

The current limiter circuit limits the drive current to a current determined by the equation I = VRF/RF, where VRF =

0.25V (typical) and Rf is the current detection resistor. The limiting operation works by reducing other output on duty

to suppress the drive current.

Detection with excellent precision can be acquired by connecting the RF and RFGND pin lines to points as close as

possible to the ends of the current detection resistor (Rf).

4. Reference clock

Care must be taken to assure that no noise due to chattering or other problems appears on the externally input clock

signal. While the input circuit is designed with hysteresis, noise must be rejected by, for example, inserting capacitors

in the clock line if noise problems occur.

If the application is to be started in the state where there is no reference clock input signal, the motor will turn

somewhat and then drive will be turned off.

5. PWM frequency

The PWM frequency is determined by the capacitance of the capacitor (C) connected to the PWM pin.

fPWM ≈ 1/(30000 × C)

If a 620pF capacitor is used, the circuit will oscillate at about 50kHz. If the PWM frequency is too low the motor will

emit switching noise, and if it is too high the power loss in the output will increase. A frequency in the range 30kHz to

100kHz is desirable. This capacitor must be connected between this pin and the GND pin by lines that are as short as

possible to make this circuit immune to noise.

6. Hall sensor input signals

To prevent noise problems, the Hall sensor input signals should have an amplitude of at least 100mV. If the output

waveforms (during phase switching) are disrupted by noise, this must be prevented by connecting capacitors across the

inputs.

If the outputs from a Hall sensor IC are input, holding one side of the inputs (either the + or - side) at a voltage within

the common-mode input range for direct Hall sensor signal input will allow the other side to be used as 0V to VCC

input.

7. FG input signal

Normally, one of the Hall sensor signals is used as the FG input signal. if noise is a problem, the input signal must be

filtered with a capacitor or a capacitor plus resistor.