CYIS1SM0250-AA
Document Number: 38-05713 Rev. *B
Page 14 of 24
Figure 11. Timing for Loading the X- and Y- Register
Other Signals
Tie SELECT signal to VDD for normal operation. This signal
was added for diagnostic reasons and inhibits the pixel array
operation when held low.
The CAL signal sets the output amplifier DC offset level. When
this signal is active (high) the pixel array is internally
disconnected from the output amplifier, its gain is set to unity
and its input signal is connected to the BLACK_REF input.
Perform this action at least once for each frame.
EOS_X, EOS_YL and EOS_YR produce a pulse when the
respective shift register comes at its end. These outputs are
used mainly during testing to verify proper operation of the shift
registers.
TEST DIODE and TESTPIXEL ARRAY are connections to
optical test structures that are used for electro optical
evaluation. TESTDIODE is a plain photodiode with an area of
14x5 pixels. TESTPIXEL_ARRAY is an array (14x5) of pixels
where the photodiodes are connected in parallel. These
structures measure the photocurrent of the diodes directly.
TESTPIXEL_RESET and TESTPIXEL-OUT are connections
to a single pixel that are used for testing.
Row Blanking Time
Time Available for Read Out of Row Y
Column Start
Address
LD_X
T15
T17
T16
T19
T18
T20
T21
T22
Pixel 1
Pixel 2
Pixel 3
T23
Pixel 1
Pixel 2
ADC Out
CLK ADC
Analog
Output
CLK_X
SYNC_X
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