Nexperia

NEX80806

Adaptive multi-mode flyback controller

Due to the leakage inductance of transformer, there is large ringing waveform at ZCD pin at the beginning of flyback period.

To avoid sampling at this ringing moment, a blanking time is added after the going-low of DRV signal. ZCD sampling is not

allowed until this blanking window expires.

9.3.10. Valley switching

During QR/DCM/PFM mode, once the magnetizing current decreases to zero, the primary inductor begins oscillation with

the parasitic capacitor of primary MOS. It’s desired to turn on primary MOS at the valley moment of oscillation to minimize

the switching loss. Referring to Fig. 16, when the auxiliary winding voltage becomes negative, ZCD pin is clamped at ~0 V

internally, the current flowing out of ZCD pin is detected. Once the current is larger than IZCD_VALLEY (~9 μA), that moment

is identified as a valley moment. There may be several valley moments identified before CLK signal arrives. The valley

moment just behind CLK is chosen as the moment to turn on the primary MOS.

9.3.11. Oscillator frequency

As FB voltage decreases, the clamp frequency CLK will decrease from the maximum switching frequency FMAX to the

minimum limit FMIN (typically 25 kHz , to avoid audible noise), to optimize the efficiency for different load condition.

To optimize the EMI performance, spread-spectrum function is implemented.

9.3.12. Peak load mode

Some applications require a much higher output current, normally double the full load current, in a short period (less than

200 ms normally). The output voltage must be basically stable during this short period (output voltage is allowed to drop

~10%).

For NEX80806, the primary peak current reaches its maximum limit when the voltage on FB approaches ~2 V. The switching

frequency is also at maximum frequency FMAX (~65 kHz) at this moment. To further improve the capability of output power,

NEX80806 implemented peak load mode by increasing frequency gradually from FMAX to FPeak (~130 kHz) as FB voltage

approaches 3.2 V.

9.3.13. Driver

The typical high level of DRV pin is clamped by an internal voltage clamp which clamps the voltage at 11.5 V under normal

conditions. For a normal 12 V VCC supply, the DRV amplitude is guaranteed to be higher than 8 V. This gives enough

voltage to fully turn on the high-voltage MOSFETs, while providing an adequate margin to avoid overvoltage damage of the

gate, since most high-voltage MOSFETs have a maximum gate voltage rating of 20 V.

9.3.14. Restart

When restart process is triggered, the DRV pulse is stopped at first, the VCC voltage declines since there is no supply from

auxiliary winding. Once VCC voltage drops below VCC_OFF threshold, the device is disabled and the VCC current consumption

drops to ISTARTUP which is 5 μA typical, then VCC capacitor will be charged up by startup resistor. When VCC voltage rises

above VCC_ON, a soft start process is initiated if the line voltage meets the brown-in requirement.

9.3.15. Overload protection (OLP)

If the load current is higher than the maximum allowed output current limit, the output voltage will drop, FB voltage will

increase. If FB voltage is higher than VFB_OLP (3.5 V typical) for a period tD_OLP, overload protection is triggered, the device

will restart.

9.3.16. Over current protection (OCP)

To meet the Limited Power Source (LPS) requirements, the maximum output current of power supply should be less than

8A, and the output power should not exceed 100W at any condition. However, with a fixed primary peak current limit, the

output current and output power will increase as input line voltage increase, LPS is highly possible to be violated.

NEX80806

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Product data sheet

Rev. 2 — 28 October 2024

13 / 20