AN1759 datasheet(5/24 Pages) FREESCALE

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Application Note

DS1307 Hardware Interface

AN1759

Block Diagram

Figure 2. DS1307 Block Diagram

Serial Interface

The DS1307 supports the bidirectional, 2-wire protocol. The protocol has

these characteristics:

• Any device sending out data is defined as a transmitter.

• Any device receiving data is defined as a receiver.

• The device controlling the transfer is called the master.

• The device being controlled is called the slave.

• The master initiates all transactions.

• The master always provides the clock for both transmit and

receive operations.

• The DS1307 is always considered the slave.

• The clock signal is called SCL.

• The data signal is called SDA.

• All data is sent most significant bit (MSB) first.

Figure 3

shows the 2-wire bus interface between a master and slave.

SQUARE

OSCILLATOR

& DIVIDER

SERIAL

BUS INTERFACE

POWER

CONTROL

ADDRESS

REAL-TIME

CLOCK RAM

RAM

56 X 8

VDD

VBAT

GND

SQW/OUT

SDA

SCL

CONTROL

WAVE OUT

LOGIC

Freescale Semiconductor, Inc.

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