AS7C1028

12/5/06; V.1.0

Alliance Memory

P. 6 of 8

®

AC test conditions

Notes:

1

2

This parameter is sampled, but not 100% tested.

3

For test conditions, see AC Test Conditions, Figures A, B, C.

4

These parameters are specified with CL = 5pF, as in Figures B or C. Transition is measured

5

This parameter is guaranteed, but not tested.

6

WE is High for read cycle.

7

CE and OE are Low for read cycle.

8

Address valid prior to or coincident with CE transition Low.

9

All read cycle timings are referenced from the last valid address to the first transitioning address.

10 CE or WE must be High during address transitions. Either CE or WE asserting high terminates a write cycle.

11

All write cycle timings are referenced from the last valid address to the first transitioning address.

12 CE1 and CE2 have identical timing.

13 C=30pF, except on High Z and Low Z parameters, where C=5pF.

350

Ω

C(13)

320

Ω

GND

168

Ω

+1.72V (5V)

Figure C: Output load

255

Ω

C(13)

480

Ω

GND

+5V

Figure B: Output load

Thevenin equivalent

- Output load: see Figure B or Figure C.

- Input rise and fall times: 3 ns. See Figure A.

- Input and output timing reference levels: 1.5V.

10%

90%

10%

90%

GND

Figure A: Input pulse

3 ns