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AS7C4098A Datasheet(PDF) 5 Page - Alliance Semiconductor Corporation

Part # AS7C4098A
Description  5.0 V 256 K 횞 16 CMOS SRAM
PDF  11 Pages
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Manufacturer  ALSC [Alliance Semiconductor Corporation]
Direct Link  https://www.alliancememory.com
Logo ALSC - Alliance Semiconductor Corporation

AS7C4098A Datasheet(HTML) 5 Page - Alliance Semiconductor Corporation

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AS7C4098A
2/21/06, v 1.2
Alliance Semiconductor
P. 5 of 11
Read waveform 2 (CE, OE, UB, LB controlled)5,7,8
Write cycle (over the operating range)9
Parameter
Symbol
–10
–12
–15
–20
Unit Note
Min
Max
Min
Max
Min
Max
Min
Max
Write cycle time
tWC
10–12–15
–
20
–
ns
Chip enable (CE) to write end
tCW
7–8
–
10
–
12
–ns
Address setup to write end
tAW
7–8
–
10
–
12
–ns
Address setup time
tAS
0
–
0
–
0–0–
ns
Write pulse width (OE = High)
tWP1
7–8
–
10
–
12
–ns
Write pulse width (OE = Low)
tWP2
10–12–15
–
20
–
ns
Write recovery time
tWR
0
–
0
–
0–0–
ns
Address hold from end of write
tAH
0
–
0
–
0–0–
ns
Data valid to write end
tDW
5
–
6
7–9–
ns
Data hold time
tDH
0
–
0
–
0–0–
ns
3, 4
Write enable to output in High-Z
tWZ
2
5
2
6
2729
ns
3, 4
Output active from write end
tOW
3
–
3
–
3–3–
ns
3, 4
Byte enable Low to write end
tBW
7–8
–
10
–
12
–ns
3, 4
Data valid
tRC
tAA
tBLZ
tBA
tOE
tOLZ
tOH
tOHZ
tCHZ
tBHZ
tACE
tCLZ
Address
OE
CE
LB, UB
DataOUT



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