Electronic Components Datasheet Search
  English  ▼

X  

Preview PDF HTML

SI3201-FS Datasheet(PDF) 21 Page - Silicon Laboratories

Part # SI3201-FS
Description  PROSLIC짰 PROGRAMMABLE CMOS SLIC WITH RINGING/BATTERY VOLTAGE GENERATION
PDF  108 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  SILABS [Silicon Laboratories]
Direct Link  http://www.silabs.com
Logo SILABS - Silicon Laboratories

SI3201-FS Datasheet(HTML) 21 Page - Silicon Laboratories

Back Button SI3201-FS Datasheet HTML 17Page - Silicon Laboratories SI3201-FS Datasheet HTML 18Page - Silicon Laboratories SI3201-FS Datasheet HTML 19Page - Silicon Laboratories SI3201-FS Datasheet HTML 20Page - Silicon Laboratories SI3201-FS Datasheet HTML 21Page - Silicon Laboratories SI3201-FS Datasheet HTML 22Page - Silicon Laboratories SI3201-FS Datasheet HTML 23Page - Silicon Laboratories SI3201-FS Datasheet HTML 24Page - Silicon Laboratories SI3201-FS Datasheet HTML 25Page - Silicon Laboratories Next Button
Zoom Inzoom in Zoom Outzoom out
 21 / 108 page
background image
Si3230
Preliminary Rev. 0.96
21
Table 22. Associated Power Monitoring and Power Fault Registers
Parameter
Description/
Range
Resolution
Register
Bits
Location*
Power Monitor Pointer
0 to 5 points to Q1
to Q6, respectively
n/a
PWRMP[2:0]
Direct Register 76
Line Power Monitor Output
0 to 7.8 W for Q1,
Q2, Q5, Q6
0 to 0.9 W for Q3,
Q4
30.4 mW
3.62 mW
PWROM[7:0]
Direct Register 77
Power Alarm Threshold, Q1 & Q2
0 to 7.8 W
30.4 mW
PPT12[7:0]
Indirect Register 32
Power Alarm Threshold, Q3 & Q4
0 to 0.9 W
3.62 mW
PPT34[7:0]
Indirect Register 33
Power Alarm Threshold, Q5 & Q6
0 to 7.8 W
30.4 mW
PPT56[7:0]
Indirect Register 34
Thermal LPF Pole, Q1 & Q2
see equation above
NQ12[7:0]
Indirect Register 37
Thermal LPF Pole, Q3 & Q4
see equation above
NQ34[7:0]
Indirect Register 38
Thermal LPF Pole, Q5 & Q6
see equation above
NQ56[7:0]
Indirect Register 39
Power Alarm Interrupt Pending
Bits 2 to 7 corre-
spond to Q1 to Q6,
respectively
n/a
QnAP[n+1],
where n = 1 to 6
Direct Register 19
Power Alarm Interrupt Enable
Bits 2 to 7 corre-
spond to Q1 to Q6,
respectively
n/a
QnAE[n+1],
where n = 1 to 6
Direct Register 22
Power Alarm
Automatic/Manual Detect
0 = manual mode
1 = enter open state
upon power alarm
n/a
AOPN
Direct Register 67
*Note:
The ProSLIC uses registers that are both directly and indirectly mapped. A “direct” register is one that is mapped
directly. An “indirect” register is one that is accessed using the indirect access registers (direct registers 28 through
31).



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com