data sheet

• Up to 176 ball count

• 7-12 mm body size

• Thinnest CSP available at 0.5 mm max mounted height

• JEDEC Level 1 Reliability to 260 °C reflow temperature

• Conventional process flow with proven wirebond technology

• Standardized footprints at 0.5 mm pitch

• Package stacking potential of tested packages

• Two stacked die potential

12 x 12 mm body; 176 I/O; Typical 39 °C/W

applications. Higher thermal performance can be achieved by

adding a heat spreader or heat sink to the die's exposed

backside. In addition, future die-up configurations will provide

a direct heat dissipation path into the product motherboard

through the die backside.

Min

Max

Inductance (nH)

0.735

1.546

Capacitance (pF)

0.176

0.319

Resistance (mOhms)

47.9

89.83

Package Dimensions:

7 x 7 mm body; 89 I/O; 0.3 mm ball diameter; 100 MHz

Package Level*:

• Moisture sensitivity

JEDEC Level 1 @ 260 °C

• Temp Cycle

-55° C/+125 °C, 1000 cycles

• Temp/Humidity

85 °C/ 85% RH, 1000 hrs

• High Temp Storage

150 °C, 1000 hrs

• PCT/HAST

130 °C, 85% RH, 96 hrs

*Data for 12 x 12 mm body; 176 I/O; 7.62 mm DC die,

0.15 mm thick

Board Level:

• Thermal cycle

-55 °C / 125 °C 2 cycles / hour,

1000 cycles

• First failure 1100 cycles

• Lead free solder

capable of an extremely thin 0.5 mm maximum

mounted height. This package can squeeze into

applications requiring a thin form factor. The

et

IC processing including standard wire bonding,

molding and substrate infrastructure. The resulting

package consists of one or two peripheral rows of

0.3 mm diameter solder balls to allow common

SMT processing.

There are many advantages as a direct result of the

0.5 mm mounted height of the package, the result of

solder ball diameter and thin core laminate substrate.

Every other aspect of the package, die, wires and

moldcap are within the dimensions of the substrate

design is the superior moisture resistance. Since

die attach materials are not used to mount the

die, there is reduced capability to trap moisture.

Therefore, popcorn induced delamination is reduced.

capability of stacking completely tested packages,

i.e., packaged memory, into a single footprint on the

motherboard. In this manner, two stacked etCSP™

packages can be tested before mounting and the

combined height is less than 1.0 mm.

LAMINATE

www.amkor.com

DS578F

Rev Date: 07’03

Features:

Thermal Performance:

Electrical:

Reliability:

Applications:

drives, thin wireless handsets, Flash or EEPROM memory and other portable products where vertical

with proper substrate designs. This creates an opportunity to multiply memory capacity without

increasing board area.

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TO VIEW THE MOST CURRENT PRODUCT INFORMATION

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