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STM32F103C8 Datasheet(PDF) 51 Page - STMicroelectronics |
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STM32F103C8 Datasheet(HTML) 51 Page - STMicroelectronics |
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51 / 67 page  STM32F103xx Electrical characteristics 51/67 SPI interface characteristics Unless otherwise specified, the parameters given in Table 36 are derived from tests performed under ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 7. Refer to Section 5.3.12: I/O port pin characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO). Table 36. SPI characteristics(1) 1. TBD = to be determined. Symbol Parameter Conditions Min Max Unit fSCK 1/tc(SCK) SPI clock frequency Master mode TBD TBD MHz Slave mode 0 TBD tr(SCK) tf(SCK) SPI clock rise and fall time Capacitive load: C=50 pF TBD ns tsu(NSS) (2) 2. Values based on design simulation and/or characterization results, and not tested in production. NSS setup time Slave mode 0 th(NSS) (2) NSS hold time Slave mode 0 tw(SCKH) (2) tw(SCKL) (2) SCK high and low time Master mode, fPCLK= TBD, presc = TBD TBD tsu(MI) (2) tsu(SI) (2) Data input setup time Master mode TBD Slave mode TBD th(MI) (2) th(SI) (2) Data input hold time Master mode TBD Slave mode TBD Master mode, fPCLK= TBD TBD(3) 3. Depends on fPCLK. For example, if fPCLK= 8MHz, then tPCLK = 1/fPLCLK =125 ns and tv(MO) = 255 ns. Slave mode, fPCLK= TBD TBD(3) ta(SO) (2)(4) 4. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. Data output access time Slave mode TBD TBD Slave mode, fPCLK= TBD TBD TBD tdis(SO) (2)(5) 5. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z Data output disable time Slave mode TBD TBD tv(SO) (2)(1) Data output valid time Slave mode (after enable edge) TBD fPCLK= TBD TBD tv(MO) (2)(1) Data output valid time Master mode (after enable edge) TBD fPCLK= TBD TBD TBD th(SO) (2) Data output hold time Slave mode (after enable edge) TBD th(MO) (2) Master mode (after enable edge) TBD |
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