SN54ACT8990, SN74ACT8990

TEST-BUS CONTROLLERS

IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 16-BIT GENERIC HOST INTERFACES

SCAS190E – JUNE 1990 – REVISED JANUARY 1997

11

POST OFFICE BOX 655303

PARAMETER MEASUREMENT INFORMATION

th

tsu

From Output

Under Test

CL = 50 pF

LOAD CIRCUIT

S1

VCC

Open

GND

1 k

Ω

tPLH/tPHL

tPLZ/tPZL

tPHZ/tPZH

Open

VCC

GND

Output

Control

(high-level

enabling)

Output

Waveform 1

S1 at VCC

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

VOL

VOH

tPZL

tPZH

tPLZ

tPHZ

1.5 V

1.5 V

≈ VCC

0 V

50% VCC

≈ 0 V

3 V

Data Input

Timing Input

1.5 V

3 V

0 V

1.5 V

1.5 V

3 V

0 V

3 V

0 V

1.5 V

1.5 V

tw

Input

(see Note A)

50% VCC

10% VCC

90% VCC

tPLH

tPHL

1.5 V

1.5 V

3 V

0 V

50% VCC

50% VCC

VOH

VOL

Input

Output

VOLTAGE WAVEFORMS

PULSE DURATION

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

TEST

S1

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR

≤ 10 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.

For testing pulse duration: tr = tf = 1 to 3 ns. Pulse polarity can be either high-to-low-to-high or low-to-high-to-low.

D. The outputs are measured one at a time with one transition per measurement.

Figure 1. Load Circuit and Voltage Waveforms