AL4V183 datasheet(2/2 Pages) AVERLOGIC

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AVERLOGIC TECHNOLOGIES, INC.

TEL

: 1 408 361-0400

e-mail: sales_usa@averlogic.com URL: www.averlogic.com

AVERLOGIC TECHNOLOGIES, CORP. TEL: 886 2-87523988 e-mail: sales@averlogic.com.tw URL: www.averlogic.com.tw

October 30, 2004

(1k , 4k) x18

Memory

Array

Input

Buffer

Output

Buffer

Write

Control

Logic

Read

Control

Logic

Timing &

Control Logic

Write Pointer

Read Pointer

Offset

Regissers

Input data bus

Output data bus

/OE

WCLK

/WEN

RCLK

/REN

/BEB

/IW

/OW

Figure 1. AL4V18x FIFO Block Diagram

/RRSTB

/WRSTB

The

18bit

input

and

output

ports

operate

independently at a maximum speed of 100 MHz.

The

built-in

address

decoder

and

pointer

managing circuits provide a straightforward bus

interface to serially read/write memory that

reduces inter-chip design efforts. The AL4V18x

embedded memory array and high performance

process technologies with extended controller

functions (read skip, fixed and programmable

status

flags...

etc.)

offer

flexible

memory

management.

These FIFOs support up to 18-bit input and output

data bus-width that is controlled by separate clock

and enable signals respectively. The input data is

acquired at each rising edge of a free running

write clock while a write enable control pin is

asserted. The output data is available after each

rising edge of a free running read clock while a

read enable and output enable control pins are

asserted. When output enable (/OE) is LOW, the

data output bus is active. If /OE is HIGH, the

output data bus will be in a high-impedance. This

signal can control whether the data is going to be

skipped during the read operation.

Bus-Matching feature can flexibly configure input

and output bus width. The chip can automatically

convert the input data bus width to match up

output data bus width by packing or unpacking

the data. A Big-Endian/Little-Endian data word

format is provided to invert the read-in bytes

sequence for output. And the Retransmit function

allows data to be reread from the FIFO more than

once.

These chips are available as a 64pin STQFP

Package.

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